Semiconductor device

• US 9,748,349 B2
• Filed: 05/28/2015
• Issued: 08/29/2017
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lu, Chia-Lin, Chen, Chun-Lung, Liao, Kun-Yuan, Chang, Feng-Yi, Chen, Chieh-Te, Huang, Wei-Hao
• Primary Examiner(s): Coleman, William
• Assistant Examiner(s): LY, KIEN C
• Application Number:
  US14/723,467
• Publication Number:
  US 20160322468A1
• Time in Patent Office: 824 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate, wherein a bottom surface of the gate structure is even with a top surface of the substrate;

a source/drain region adjacent to two sides of the gate structure;

an interlayer dielectric (ILD) layer around the gate structure;

a first dielectric layer on top of the ILD layer;

a first contact plug in the ILD layer and contacting the first dielectric layer and the source/drain region directly;

a second dielectric layer on the ILD layer;

a second contact plug in the second dielectric layer and contacting the first contact plug and the gate structure directly, wherein the second contact plug is disposed on top of the gate structure and the source/drain region; and

a spacer on the first dielectric layer and between the second contact plug and the second dielectric layer;

wherein a bottom surface of the first dielectric layer contacts a top surface of the ILD layer and a top surface of the gate structure directly.

2. The semiconductor device of claim 1, further comprising:

a stop layer on the first dielectric layer; and

the second contact plug in the stop layer, the first dielectric layer, and the second dielectric layer.

3. The semiconductor device of claim 2, wherein the stop layer comprises silicon nitride.

4. The semiconductor device of claim 2, wherein the stop layer contacts the spacer, the first dielectric layer, and the second dielectric layer directly.

5. The semiconductor device of claim 1, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

6. The semiconductor device of claim 1, wherein the spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

7. The semiconductor device of claim 1, further comprising a truncated spacer in the second dielectric layer and between the first contact plug and the gate structure.

8. The semiconductor device of claim 7, wherein two sidewalls of the truncated spacer contact the second contact plug directly.

9. The semiconductor device of claim 7, wherein a sidewall of the truncated spacer is aligned with an edge of the first contact plug.

10. The semiconductor device of claim 1, wherein the first contact plug contacts the ILD layer directly.

11. The semiconductor device of claim 1, wherein the spacer contacts the second dielectric layer directly.

12. The semiconductor device of claim 1, wherein the top surfaces of the first contact plug and the first dielectric layer are coplanar.