Threshold adjustment for quantum dot array devices with metal source and drain

• US 9,748,356 B2
• Filed: 06/28/2013
• Issued: 08/29/2017
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US13/931,234
• Publication Number:
  US 20140084247A1
• Time in Patent Office: 1,523 Days
• Field of Search: 257 24, 438 7
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V_t. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease V_t. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies V_t. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a recessed metal gate in the semiconductor substrate;

a source region in the semiconductor substrate, the source region including a first quantum dot that is a metal, the source region including a first recess;

a drain region in the semiconductor substrate, the drain region including a second quantum dot that is a metal, the drain region including a second recess;

a channel region coupled between the source and drain regions, the recessed metal gate and portions of the channel region having co-planar upper surfaces, the first and second quantum dots having a molecular composition that includes clusters of monomers;

a first silicide layer lining bottom and side walls of the first recess, the first quantum dot being positioned in the first recess and being surrounded by the first silicide layer; and

a second silicide layer lining bottom and side walls of the second recess, the second quantum dot being positioned in the second recess and being surrounded by the second silicide layer.

2. The semiconductor device of claim 1 wherein the monomers are cations.

3. The semiconductor device of claim 1 wherein the monomers are anions.

4. The semiconductor device of claim 1 wherein the clusters of monomers are electrically neutral.

5. The semiconductor device of claim 1 wherein the gate is made of a work function material including a layer that contains one or more of TiW, TiC, and TiN.

6. The semiconductor device of claim 1, further comprising a gate dielectric layer positioned in a third recess formed in the substrate, the channel region including an epitaxial layer lining walls of the third recess, the gate dielectric layer lining internal walls of the epitaxial layer, and the recessed metal gate including a metal liner material positioned in the third recess and lining internal walls of the epitaxial layer.

7. A transistor comprising:

a semiconductor substrate;

a doped source region in the semiconductor substrate, the doped source region including a first recess, a first embedded quantum dot that is a metal in the first recess, the first embedded quantum dot containing clusters of monomers having a selected cluster size that alters an energy gap of the silicon and determines a threshold voltage of the transistor;

a doped drain region in the semiconductor substrate, the doped drain region including a second recess, a second embedded quantum dot that is a metal in the second recess, the second embedded quantum dot containing clusters of monomers having a selected cluster size that alters an energy gap of the silicon and determines a threshold voltage of the transistor;

a channel region coupling the doped source and drain regions;

a recessed metal gate adjacent to the channel region in the semiconductor substrate;

a first silicide layer lining bottom and side walls of the first recess, the first embedded quantum dot being positioned in the first recess and being surrounded by the first silicide layer; and

a second silicide layer lining bottom and side walls of a second recess, the second embedded quantum dot being positioned in the second recess and being surrounded by the second silicide layer.

8. The transistor of claim 7 wherein the channel region is made of an epitaxial material.

9. The transistor of claim 8 wherein the epitaxial material is one or more of Ge or SiGe.

10. The transistor of claim 7, further comprising a gate dielectric layer positioned in a third recess formed in the substrate, the channel region including an epitaxial layer lining walls of the third recess, the gate dielectric layer lining internal walls of the epitaxial layer, and the recessed metal gate including a metal liner material positioned in the third recess and lining internal walls of the gate dielectric layer.

11. The transistor of claim 7 wherein the source region, drain region, and recessed metal gate are co-planar with a top surface of the silicon substrate.

12. An electronic device comprising:

a silicon substrate;

a plurality of n-type field effect transistors having n-doped source and drain regions, each n-doped source and drain region including a first recess, each first recess including a first silicide layer lining bottom and side walls of the first recess, each first silicide layer surrounding a first embedded silver bromide quantum dot; and

a plurality of p-type field effect transistors having p-doped source and drain regions, each p-doped source and drain region including a second recess, each second recess including a second silicide layer lining bottom and side walls of the second recess, each second silicide layer surrounding a second embedded silver bromide quantum dot.

13. The device of claim 12 wherein the transistors further include recessed metal gates co-planar with a top surface of the silicon substrate.

14. The device of claim 12 wherein the n-doped source and drain regions and the p-doped source and drain regions further include doped epitaxial materials.

15. The device of claim 12 wherein the first and second embedded silver bromide quantum dots have a shape that includes one or more of a circle, ellipse, oval, or polygon.

16. The device of claim 12 wherein the plurality of n-type field effect transistors and the plurality of p-type field effect transistors are arranged in a densely-packed offset array.

17. The device of claim 12, wherein each transistor of the plurality of n-type field effect transistors and the plurality of p-type field effect transistors includes:

a third recess in the silicon substrate;

a channel region coupling the respective source and drain regions of each transistor, the channel region including an epitaxial layer lining walls of the third recess; and

a gate formed in the third recess, the gate including a gate dielectric layer lining internal walls of the epitaxial layer, and a recessed metal liner material positioned in the third recess and lining internal walls of the gate dielectric layer.