Tunnel field-effect transistor (TFET) with supersteep sub-threshold swing

• US 9,748,368 B2
• Filed: 08/23/2013
• Issued: 08/29/2017
• Est. Priority Date: 07/03/2013
• Status: Expired due to Fees

• Current Assignee: University of Calcutta
• Original Assignee: University of Calcutta
• Inventors: Mallik, Abhijit
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US14/902,480
• Publication Number:
  US 20160141398A1
• Time in Patent Office: 1,467 Days
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (V_DD) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current I_ON. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow.

Claims

1. A tunnel field-effect transistor (FET) device, comprising:

a bulk silicon substrate;

a p-i-n tunnel structure formed within the bulk silicon substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the bulk silicon substrate between the drain region and the source region, wherein the drain region comprises silicon or silicon-germanium doped with dopants of the second type, and wherein the bulk silicon substrate comprises silicon or silicon-germanium doped with dopants of either the first type the second type;

a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region;

a source electrode;

a drain electrode;

a first side-wall spacer material arranged to interface with each of a first portion of the source region and a portion of the source electrode; and

a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode.

2. The tunnel FET device according to claim 1, wherein each of the first side-wall spacer material and the second side-wall spacer material is further arranged to substantially surround the gate electrode and the gate dielectric.

3. The tunnel FET device according to claim 1, wherein the drain electrode is configured to interface with each of the portion of the drain region and a portion of the second side-wall spacer material.

4. The tunnel FET device according to claim 1, wherein the source electrode is configured to interface with each of the first portion of the source region and a portion of the first side-wall spacer material.

5. The tunnel FET device according to claim 1, wherein each of the fir side-wall spacer material and the second side-wall spacer material has a width in a range between about 5 nm and about 15 nm.

6. The tunnel FET device according to claim 1, wherein the source region comprises germanium (Ge), silicon-germanium (SiGe), indium-arsenide (InAs), or indium-gallium-arsenide (InGaAs) doped with the dopants of the first type.

7. The tunnel FET device according to claim 1, wherein the dopants of the first type include n-type dopants and the dopants of the second type include p-type dopants.

8. The tunnel FET device according to claim 1, wherein

a second portion of the source region has a first thickness in a range between about 10 nm and about 40 nm, and wherein a third portion of the source region has a second thickness in a range between about 15 nm and about 60 nm;

the gate electrode has a width in a range between about 10 nm and about 100 nm;

the gate dielectric has a thickness in a range between about 0.4 nm and about 5 nm; and

the channel region has a width in a range between about 6 nm and about 30 nm and overlap between the channel region and the gate dielectric is in a range between about 3 nm and 10 nm.

9. A tunnel field-effect transistor (FET) device, comprising:

a substrate;

a p-i-n tunnel structure formed within the substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the substrate between the drain region and the source region;

a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region;

a source electrode;

a drain electrode;

a first side-wall spacer material arranged to interface with each of a portion of the source region and a portion of the source electrode; and

a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode,

wherein each of the first side-wall spacer material and the second side-wall spacer material is further arranged to substantially surround the gate electrode and the gate dielectric.

10. The tunnel FET device according to claim 9, wherein the gate dielectric comprises a hafnium based oxide, a silicon based oxide, a silicon based nitride, or a high-k gate dielectric, and wherein each of the first side-wall spacer material and the second side-wall spacer material comprises a silicon based oxide, silicon nitride, or a low-k dielectric.

11. The tunnel FET device according to claim 10, wherein the gate dielectric comprises a hafnium dioxide having a thickness of about 0.6 nm.

12. The tunnel FET device according to claim 9, wherein the gate electrode has a width of about 30 nm.

13. The tunnel FET device according to claim 9, wherein each of the first side-wall spacer material and the second side-wall spacer material has a width of about 10 nm.

14. The tunnel FET device according to claim 9, wherein the channel region has a width of about 10 nm.