Tunnel field-effect transistor (TFET) with supersteep sub-threshold swing
First Claim
1. A tunnel field-effect transistor (FET) device, comprising:
- a bulk silicon substrate;
a p-i-n tunnel structure formed within the bulk silicon substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the bulk silicon substrate between the drain region and the source region, wherein the drain region comprises silicon or silicon-germanium doped with dopants of the second type, and wherein the bulk silicon substrate comprises silicon or silicon-germanium doped with dopants of either the first type the second type;
a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region;
a source electrode;
a drain electrode;
a first side-wall spacer material arranged to interface with each of a first portion of the source region and a portion of the source electrode; and
a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode.
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Accused Products
Abstract
Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (VDD) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current ION. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow.
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Citations
14 Claims
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1. A tunnel field-effect transistor (FET) device, comprising:
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a bulk silicon substrate; a p-i-n tunnel structure formed within the bulk silicon substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the bulk silicon substrate between the drain region and the source region, wherein the drain region comprises silicon or silicon-germanium doped with dopants of the second type, and wherein the bulk silicon substrate comprises silicon or silicon-germanium doped with dopants of either the first type the second type; a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region; a source electrode; a drain electrode; a first side-wall spacer material arranged to interface with each of a first portion of the source region and a portion of the source electrode; and a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A tunnel field-effect transistor (FET) device, comprising:
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a substrate; a p-i-n tunnel structure formed within the substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the substrate between the drain region and the source region; a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region; a source electrode; a drain electrode; a first side-wall spacer material arranged to interface with each of a portion of the source region and a portion of the source electrode; and a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode, wherein each of the first side-wall spacer material and the second side-wall spacer material is further arranged to substantially surround the gate electrode and the gate dielectric. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification