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Solar cell and method for producing same

  • US 9,748,418 B2
  • Filed: 05/25/2012
  • Issued: 08/29/2017
  • Est. Priority Date: 05/27/2011
  • Status: Active Grant
First Claim
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1. A rear contacted heterojunction intrinsic thin layer solar cell comprising:

  • a silicon substrate with a front surface and a rear surface;

    a passivating layer at the front surface of the silicon substrate;

    a continuous thin intrinsic amorphous silicon layer covering the entire rear surface of the substrate, the intrinsic amorphous silicon layer having a front surface adjacent to the rear surface of the silicon substrate and the intrinsic amorphous silicon layer having a back surface opposite to the front surface of the intrinsic amorphous silicon layer;

    an emitter layer comprising a doped semiconducting material of a first doping polarity and covering one or more portions of the back surface of the intrinsic amorphous silicon layer;

    a base layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and with higher doping concentration than the silicon substrate and covering one or more portions of the back surface of the intrinsic amorphous silicon layer neighboring the portion covered by the emitter layer;

    a separating layer comprising an electrically insulating material and being arranged on one or more portions of the back surface of the intrinsic amorphous silicon layer laterally between neighboring portions of the emitter layer and portions of the base layer;

    whereinadjacent regions of the emitter layer and the separating layer and adjacent regions of the base layer and the separating layer are partially laterally overlapping in such a way that, in an overlapping area, at least a portion of the separating layer is located closer to the substrate than an overlapping portion of a respective one of the emitter layer and the base layer, and that the separating layer comprises a first portion that is arranged between the silicon substrate and the base layer and a second portion that is arranged between the silicon substrate and the emitter layer.

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