Peaking inductor array for peaking control unit of transceiver

• US 9,748,927 B2
• Filed: 09/08/2016
• Issued: 08/29/2017
• Est. Priority Date: 08/03/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Francese, Pier A., Prasad, Mangal, Tran, Hung H., Yuan, Xiaobin
• Primary Examiner(s): Takaoka, Dean
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US15/259,475
• Publication Number:
  US 20170040975A1
• Time in Patent Office: 355 Days
• Field of Search: 333213, 333214, 333215
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03H 11/48 simulating reactances
• CPC Class Codes: H04B 1/12 Neutralising, balancing, or compensation arrangements
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Claims

1. A method for controlling peaking of a peaking control unit of a transceiver, the method comprising:

forming a peaking inductor array, the forming comprising;

connecting a plurality of cells in parallel, wherein each cell comprises a respective active inductor, a respective decoupling capacitor, and a respective selectable resistor, wherein each respective active inductor comprises a respective first field effect transistor (FET) and a respective second FET, and wherein each respective selectable resistor comprises a respective switch in series with a respective resistor;

connecting the respective first FET in series with the respective second FET for each respective active inductor;

connecting the respective decoupling capacitor and the respective selectable resistor for each cell in series; and

connecting each of the respective decoupling capacitor and the respective selectable resistor in parallel with the respective first FET for each cell, wherein a capacitance of the respective decoupling capacitor in each cell is larger than intrinsic and extrinsic capacitances of the respective active inductor;

providing the peaking inductor array in the peaking control unit, wherein the providing comprises connecting the peaking inductor array in parallel with a direct current (DC) diode array in the peaking control unit; and

controlling peaking of the peaking inductor array in two dimensions by opening or closing at least one respective switch.