Second order harmonic cancellation for radio frequency front-end switches

• US 9,749,003 B2
• Filed: 05/08/2014
• Issued: 08/29/2017
• Est. Priority Date: 05/08/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Zhao, Huan, Li, Qiang
• Primary Examiner(s): West, Lewis
• Application Number:
  US14/272,747
• Publication Number:
  US 20140335802A1
• Time in Patent Office: 1,209 Days
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04B 2001/485 inhibiting unwanted transmission

Abstract

A radio frequency switch circuit with improved harmonic suppression and low insertion loss has an antenna port and a plurality of signal ports. A plurality of transistor switch circuits, are connected to a respective one of the plurality of signal ports and to the antenna port. Each of the transistor switch circuits has a transistor, which in an off state, together with a harmonic suppression capacitor and a parallel inductor both connected thereto, define a tank circuit that suppresses RF signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits. The harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistor.

Claims

1. A radio frequency switch circuit, comprising:

an antenna port;

a plurality of signal ports;

a plurality of transistor switch circuits each connected to a respective one of the plurality of signal ports and to the antenna port, each of the transistor switch circuits including a transistor which in an off state, together with a harmonic suppression capacitor connected to the transistor and a parallel inductor connected across a source and a drain of the transistor, define a tank circuit that suppresses radio frequency signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits, the harmonic suppression capacitors being tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistors.

2. The radio frequency switch circuit of claim 1 wherein each of the transistor switch circuits includes a transistor activation suppression capacitor connected to the transistor and the signal port.

3. The radio frequency switch circuit of claim 2 wherein the transistor activation suppression capacitor is connected across a source and a gate of the transistor.

4. The radio frequency switch circuit of claim 2 wherein the transistor activation suppression capacitor is tuned to maximize peak power handling capacity of the transistor switch circuit.

5. The radio frequency switch circuit of claim 1 wherein each of the transistor switches define a minimal series resistance with the transistor thereof in an on state.

6. The radio frequency switch circuit of claim 1 further comprising a direct current blocking capacitor connected between each of the transistor switch circuits and the antenna port.

7. The radio frequency switch circuit of claim 1 further comprising a direct current blocking capacitor connected between each of the transistor switch circuits and the respective signal ports.

8. The radio frequency switch circuit of claim 1 wherein the transistors have an n-type metal oxide semiconductor field effect structure.

9. The radio frequency switch circuit of claim 1 wherein the signal ports and the transistor switch circuits number three to define a single pole, triple throw switch.

10. The radio frequency switch circuit of claim 1 wherein, in each of the transistor switch circuits, the harmonic suppression capacitor is connected to the drain and a body of the transistor.

11. The radio frequency switch circuit of claim 10 wherein each of the transistor switch circuits includes a transistor activation suppression capacitor connected to the transistor and the signal port.

12. The radio frequency switch circuit of claim 11 wherein, in each of the transistor switch circuits, the transistor activation suppression capacitor is connected across the source and a gate of the transistor.

13. The radio frequency switch circuit of claim 11 wherein, in each of the transistor switch circuits, the transistor activation suppression capacitor is tuned to maximize peak power handling capacity of the transistor switch circuit.

14. The radio frequency switch circuit of claim 11 wherein, in each of the transistor switch circuits, the harmonic suppression capacitor, together with the transistor activation suppression capacitor, is optimized for harmonic distortion suppression.

15. The radio frequency switch circuit of claim 10 further comprising a direct current blocking capacitor connected between each of the transistor switch circuits and the antenna port.

16. The radio frequency switch circuit of claim 10 further comprising a direct current blocking capacitor connected between each of the transistor switch circuits and the respective signal ports.

17. The radio frequency switch circuit of claim 1 wherein, in each of the transistor switch circuits, a first one of the parasitic diodes of the transistor is between the body and the drain thereof and a second one of the parasitic diodes of the transistor is between the body and the source thereof.

18. The radio frequency switch circuit of claim 17 wherein, in each of the transistor switch circuits, the tank circuit blocks a radio frequency signal at the drain of the transistor.

19. The radio frequency switch circuit of claim 1 wherein, in each of the transistor switch circuits, the source of the transistor is connected to the respective one of the plurality of signal ports and the drain is connected to the antenna port.

20. The radio frequency switch circuit of claim 1 wherein, in each of the transistor switch circuits, a gate of the transistor is connected to a respective one of a plurality of control line terminals, the transistor being selectively activatable in response to an enable signal applied to the respective one of the plurality of control line terminals.