Header parity error handling

• US 9,749,448 B2
• Filed: 11/25/2014
• Issued: 08/29/2017
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Guddeti, Jayakrishna
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/553,692
• Publication Number:
  US 20160147592A1
• Time in Patent Office: 1,008 Days
• CPC Class Codes: H04L 1/0056 Systems characterized by the type of code used H04L1/08 takes precedence
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0082 fields explicitly indicating existence of error in data being transmitted, e.g. so that downstream stations can avoid decoding erroneous packet; relays
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

Claims

1. An apparatus comprising:

a root complex device comprising;

parity error detector logic, implemented at least in part in hardware, to detect a parity error in a header, wherein the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type;

header fabricator logic, implemented at least in part in hardware, to generate fabricated header data for one or more of the plurality of fields, wherein the fabricated header data is to indicate the parity error and replace data of one or more of the plurality of fields; and

error handler logic, implemented at least in part in hardware, to enter an error containment mode based on the parity error.

2. The apparatus of claim 1, wherein at least a particular one of the fields is to be encoded with the fabricated header data to prevent an illegal value in the particular field.

3. The apparatus of claim 2, wherein the illegal value results from the parity error corrupting a value of the particular field.

4. The apparatus of claim 1, wherein the header comprises a header of a transaction layer packet.

5. The apparatus of claim 4, wherein the plurality of fields are to comprise a format field, a type field, a length field, an address field, a requester identifier field, and a tag field.

6. The apparatus of claim 5, wherein the fabricated header data is to comprise:

for the format and type fields, values corresponding to a transaction type of the particular queue;

for the length field, a first constant value; and

for the address field, a second constant value outside of system address space;

wherein values of the requester identifier field and the tag field are to be retained.

7. The apparatus of claim 6, wherein the parity error is to be identified based on the second constant value.

8. The apparatus of claim 5, wherein the plurality of fields are further to comprise a byte enable field and an error/poisoned field.

9. The apparatus of claim 8, the fabricated header data is to comprise:

for the byte enable field, a third constant value; and

for the error/poisoned field, a false value.

10. The apparatus of claim 1, wherein the fabricated header data is to maintain a value of at least a particular one of the plurality of fields.

11. The apparatus of claim 10, further comprising a filter to prevent escalation of errors resulting from fabricated header data in the particular field triggering an error at a downstream I/O device.

12. The apparatus of claim 1, wherein the particular queue comprises a header queue and, during the error containment mode, the error handler is to:

flush a data queue corresponding to the header queue;

provide credits for transactions subsequent to the parity error; and

set queue status signals for the data queue to a constant value.

13. The apparatus of claim 12, wherein the error handler, during the error containment mode, is further to handle pop requests and handle push requests.

14. The apparatus of claim 12, wherein the error handler, in response to the flush of the queue, is to return credits corresponding to transactions flushed from the data queue.

15. The apparatus of claim 1, further comprising an error reporter to log the parity error.

16. The apparatus of claim 1, wherein the error containment mode is to allow transactions pending at detection of the parity error to proceed prior to system shutdown.

17. A method comprising:

detecting, using root complex hardware, a parity error in a header, wherein the header is in a particular one of a plurality of header queues, the header is to include a plurality of fields, and each of the header queues corresponds to a respective one of a plurality of transaction types;

generating, using the root complex hardware, fabricated header data for the plurality of fields, wherein the fabricated header data is to replace data of at least one field of the particular packet with dummy data; and

entering an error containment mode based on the parity error.