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Header parity error handling

  • US 9,749,448 B2
  • Filed: 11/25/2014
  • Issued: 08/29/2017
  • Est. Priority Date: 11/25/2014
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a root complex device comprising;

    parity error detector logic, implemented at least in part in hardware, to detect a parity error in a header, wherein the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type;

    header fabricator logic, implemented at least in part in hardware, to generate fabricated header data for one or more of the plurality of fields, wherein the fabricated header data is to indicate the parity error and replace data of one or more of the plurality of fields; and

    error handler logic, implemented at least in part in hardware, to enter an error containment mode based on the parity error.

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