High speed rolling image sensor with ADM architecture and method of implementing thereof

• US 9,749,569 B2
• Filed: 12/22/2015
• Issued: 08/29/2017
• Est. Priority Date: 12/22/2015
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Mabuchi, Keiji, Manabe, Sohei
• Primary Examiner(s): Nazrul, Shahbaz
• Application Number:
  US14/979,058
• Publication Number:
  US 20170180663A1
• Time in Patent Office: 616 Days
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/44 by partially reading an SSIS array
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

High speed rolling image sensor includes pixel array disposed in first semiconductor die, readout circuits disposed in second semiconductor die and conductors. Pixel array is partitioned into pixel sub-arrays (PSAs). Each of the PSAs includes a plurality of pixels. Pixel groups include pixels that are non-contiguous, non-overlapping and distinct. Each pixel group includes pixels from different PSAs. Each pixel group is coupled to a corresponding analog-to-digital converter and memory unit tiles (ADMs) respectively included in readout circuits. ADMs respectively include (i) analog-to-digital (ADC) circuits that convert the image data from pixel groups from analog to digital to obtain ADC outputs, and (ii) memory units to store ADC outputs. Conductors are coupling pixel array to ADMs. Conductors include number of conductors per column of pixel array. Number of conductors per column of pixel array may be equal to number of pixels in PSA arranged in same column. Other embodiments are described.

Claims

1. An image sensor comprising:

a pixel array disposed in a first semiconductor die, wherein the pixel array is partitioned into a plurality of pixel sub-arrays (PSAs), wherein each one of the plurality of PSAs includes a plurality of pixels, wherein the pixel array includes a plurality of pixel groups that include pixels that are non-contiguous, wherein each pixel group includes pixels from different PSAs;

a plurality of readout circuits disposed in a second semiconductor die, wherein the plurality of readout circuits respectively include analog-to-digital converter and memory unit tiles (ADMs), wherein each one of the pixel groups is coupled to a corresponding one of the plurality of ADMs, the ADMs respectively include (i) analog-to-digital (ADC) circuits that convert the image data from the pixel groups from analog to digital to obtain ADC outputs, and (ii) memory units to store the ADC outputs; and

a plurality of conductors coupling the pixel array to the plurality of ADMs, wherein the plurality of conductors includes a number of conductors per column of the pixel array,

wherein the number of conductors per column of the pixel array is equal to the number of pixels in the PSA that are arranged in a same column.

2. The image sensor of claim 1, wherein the number of conductors is greater than or equal to four conductors.

3. The image sensor of claim 2, wherein the number of conductors is eight, wherein each eight pixel in the pixel array is coupled to a same one of the eight conductors.

4. The image sensor of claim 1, wherein the image sensor is a stacked image sensor, and wherein the pixel groups are not positioned directly above the corresponding ADMs.

5. An image sensor comprising:

a pixel array disposed in a first semiconductor die, wherein the pixel array is partitioned into a plurality of pixel sub-arrays (PSAs), wherein each one of the plurality of PSAs includes a plurality of pixels, wherein the pixel array includes a plurality of pixel groups that include pixels that are non-contiguous, non-overlapping and distinct, wherein each pixel group includes pixels from different PSAs;

a plurality of readout circuits disposed in a second semiconductor die, wherein the plurality of readout circuits respectively include analog-to-digital converter and memory unit tiles (ADMs), wherein each one of the pixel groups is coupled to a corresponding one of the plurality of ADMs, the ADMs respectively include (i) analog-to-digital (ADC) circuits that convert the image data from the pixel groups from analog to digital to obtain ADC outputs, and (ii) memory units to store the ADC outputs; and

a plurality of conductors coupling the pixel array to the plurality of ADMs, wherein the plurality of conductors includes a number of conductors per column of the pixel array, wherein the number of conductors per column of the pixel array is equal to the number of pixels in the PSA that are arranged in a same column.

6. The image sensor of claim 5, wherein the plurality of readout circuits respectively include logic circuits to process the ADC outputs from the ADCs to generate final ADC outputs, wherein the memory units store the final ADC outputs.

7. The image sensor of claim 5, further comprising:

logic circuits disposed in a third semiconductor die coupled to the readout circuits to receive and process the ADC outputs from the ADCs to generate final ADC outputs.

8. The image sensor of claim 5, wherein the number of conductors is greater than or equal to four conductors.

9. The image sensor of claim 8, wherein the number of conductors is eight, wherein each eight pixel in the pixel array is coupled to a same one of the eight conductors.

10. The image sensor of claim 5, wherein the pixel groups and the corresponding ADMs, respectively, are positioned at different locations on the first semiconductor die and the second semiconductor die.

11. The image sensor of claim 10, wherein the pixel groups are not positioned directly above the corresponding ADMs.

12. A method of implementing a high speed rolling image sensor comprising:

capturing by a pixel array image data, wherein the pixel array is disposed in a first semiconductor die, wherein the pixel array is partitioned into a plurality of pixel sub-arrays (PSAs), where the pixel array includes a plurality of pixel groups, wherein each one of the plurality of pixel groups includes a plurality of pixels that are non-contiguous, non-overlapping and distinct, wherein each pixel group includes pixels from different PSAs;

acquiring by a plurality of readout circuits disposed in a second semiconductor die the image data from the pixel array via a plurality of conductors, wherein each one of the pixel groups is coupled to a corresponding one of the plurality of analog-to-digital converter and memory unit tiles (ADMs) respectively included in readout circuits,

wherein the plurality of conductors couple the pixel array to the plurality of ADMs, wherein the plurality of conductors includes a number of conductors per column of the pixel array, wherein the number of conductors per column of the pixel array is equal to the number of pixels in the PSA that are arranged in a same column,

converting by a plurality of analog-to-digital (ADC) circuits included in the ADMs, respectively, the image data from the pixel groups from analog to digital to obtain ADC outputs; and

storing the ADC outputs from each of the ADC circuits in memory units, respectively, wherein the plurality of ADMs respectively include the memory units.

13. The method of claim 12, further comprising:

processing by logic circuits the ADC outputs from the ADCs to generate final ADC outputs, wherein the memory units store the final ADC outputs.

14. The method of claim 13, wherein the logic circuits are included in the readout circuits, respectively.

15. The method of claim 14, wherein the logic circuits are disposed in a third semiconductor die coupled to the readout circuits to receive and process the ADC outputs from the ADCs to generate final ADC outputs.

16. The method of claim 12, wherein the number of conductors is greater than or equal to four conductors.

17. The method of claim 16, wherein the number of conductors is eight, wherein each eight pixel in the pixel array is coupled to a same one of the eight conductors.

18. The method of claim 12, wherein the pixel groups and the corresponding ADMs, respectively, are positioned at different locations on the first semiconductor die and the second semiconductor die.

19. The method of claim 18, wherein the pixel groups are not positioned above the corresponding ADMs.