Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance
First Claim
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1. A low-power low-dropout (LDO) voltage regulator device, the device comprising:
- an error amplifier configured to compare a sampled portion of a regulated output voltage of the LDO voltage regulator device with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier;
a level-shifter circuit coupled to the error amplifier;
a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device; and
an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation,wherein the level-shifter circuit comprises a source follower including a PMOS transistor and is configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower.
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Abstract
A low-power low-dropout (LDO) voltage regulator device includes an error amplifier, a level-shifter circuit, and an NMOS pass transistor. The error amplifier compares a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and generates an error signal. The level-shifter circuit is coupled to the error amplifier. The NMOS pass transistor provides the regulated output voltage with low dropout operation. The level-shifter circuit can shift a voltage level of the error signal to facilitate the low dropout operation of the NMOS pass transistor.
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Citations
20 Claims
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1. A low-power low-dropout (LDO) voltage regulator device, the device comprising:
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an error amplifier configured to compare a sampled portion of a regulated output voltage of the LDO voltage regulator device with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier; a level-shifter circuit coupled to the error amplifier; a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device; and an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation, wherein the level-shifter circuit comprises a source follower including a PMOS transistor and is configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for providing a low-power low-dropout (LDO) voltage regulator, the method comprising:
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configuring an error amplifier to compare a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier; coupling a level-shifter circuit comprising a source follower including a PMOS transistor to the error amplifier; coupling a fast loop comprising a current mirror and a gain boosting circuit to the level-shifter circuit and configuring the fast loop to improve a transient response-time and a slew rate of the LDO voltage regulator; and configuring an NMOS pass transistor to provide the regulated output voltage with low dropout operation; and configuring the level-shifter circuit to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A communication device, comprising:
a low-power low-dropout (LDO) voltage regulator device comprising; an error amplifier configured to generate an error signal at a single-ended output node of the error amplifier based on a comparison between a sampled portion of a regulated output voltage of the LDO voltage regulator and a reference voltage; an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation; a level-shifter circuit coupled to the error amplifier and the NMOS pass transistor and configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein the level-shifter circuit comprises a source follower including a PMOS transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower; and a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device. - View Dependent Claims (16, 17, 18, 19, 20)
Specification