Memory controller load balancing with configurable striping domains

• US 9,753,854 B1
• Filed: 06/23/2015
• Issued: 09/05/2017
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Inventors: Bao, Liewei
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US14/747,044
• Time in Patent Office: 805 Days
• CPC Class Codes: G06F 11/1482 by means of middleware or OS functionality
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 : being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 15/16 : Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/8023 : Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 21/79 : in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/452 : Instruction code
• CPC Class Codes: G06F 2212/502 : using adaptive policy
• CPC Class Codes: G06F 2212/601 : Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/6032 : Way prediction in set-associative cache
• CPC Class Codes: G06F 2212/621 : Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/3004 : to perform operations on memory
• CPC Class Codes: G06F 9/4825 : Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/4881 : Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5022 : Mechanisms to release resources
• CPC Class Codes: G06F 9/544 : Buffers; Shared memory; Pipes
• CPC Class Codes: H04L 45/08 : Learning-based routing, e.g. using neural networks or artificial intelligence
• CPC Class Codes: H04L 45/22 : Alternate routing
• CPC Class Codes: H04L 45/28 : using route fault recovery
• CPC Class Codes: H04L 47/83 : based on usage prediction
• CPC Class Codes: H04L 49/109 : Integrated on microchip, e.g. switch-on-chip

Abstract

Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

Claims

1. A method for managing data in a computing system comprising a plurality of cores, the method comprising:

defining striping domains among a plurality of memory controllers in the computing system, to balance workloads within at least one of the defined striping domains;

configuring by system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application executing in the computing system to balance workloads within the one or more striping domains during execution of the application;

assigning an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assigning based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;

receiving a memory access request at one of the cores to access data stored at the address; and

determining in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.

2. The method of claim 1, wherein the address includes the one or more highest order bits, which are adjacent to one or more bits that include the designated portion of the address, which are adjacent to the bits that correspond to a cache line, which are adjacent to one or more bits that correspond to a slot within the cache line.

3. The method of claim 2, wherein the one or more of the highest order bits and the bits that include the designated portion of the address, identify a memory page that includes the address.

4. The method of claim 1, wherein the address within the memory address space is a physical address translated from a virtual address.

5. The method of claim 1, wherein the application is a first application, and the striping domain is configured by the system software for corresponding applications including the first application executing on the computing system.

6. The method of claim 5, wherein the partitioned address space is partitioned into a plurality of logical memory partitions and one or more bits of the designated portion of the address together with one or more of the customizable striping mode bits determines the memory controller.

7. The method of claim 6, wherein each memory controller is coupled to memory storing data values that have addresses of a corresponding physical memory partition.

8. The method of claim 1, wherein the system address space is partitioned into a plurality of logical memory partitions and determining which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address comprises:

mapping addresses included in a given logical memory partition to different respective physical memory partitions of the plurality of memory controllers according to a mapping function that is based at least partially on the customizable striping mode bits.

9. The method of claim 8, wherein mapping further comprises;

applying a hash function applied to the one or more bits of the designated portion of the address that determine one of the logical memory partition that includes the address.

10. The method of claim 9 wherein the hash function uses the one or more bits of the designated portion of the address and additional information other than the one or more highest order bits and the bits that correspond to a cache line associated with the memory address.

11. The method of claim 10, wherein the other information comprises information stored in a register in the core at which the memory access request is received.

12. The method of claim 10, wherein the other information comprises one or more bits of the address other than the one or more highest order bits and the bits that correspond to a cache line associated with the memory address.

13. The method of claim 10, wherein the other information comprises information identifying one of the cores.

14. The method of claim 8, wherein mapping load balances memory access requests among the plurality of memory controllers.

15. The method of claim 8, wherein mapping maps addresses included in a given logical memory partition to different respective physical memory partitions of the plurality of memory controllers so that addresses associated with a first process executing on at least one of the cores are mapped to a different physical memory partition than addresses associated with a second process executing on at least one of the cores.

16. The method of claim 8, wherein mapping maps addresses included in a given logical memory partition to different respective physical memory partitions of the plurality of memory controllers so that a first memory controller that is faster than a second memory controller has more addresses mapped to its physical memory partition than the addresses mapped to the physical memory partition of the second memory controller.

17. The method of claim 1, wherein the plurality of memory controllers is a subset of fewer than all of the memory controllers coupled the computing system.

18. An integrated circuit that executes system software for configuring a computing system comprising a plurality of cores for causing the computing system to:

define striping domains among a plurality of memory controllers of the computing system, to balance workloads within at least one of the defined striping domains;

configure by the system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application to execute on the computing system to balance workloads within the one or more striping domains during execution of the application;

assign an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assignment based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;

receive a memory access request at one of the cores to access data stored at the address; and

determine, in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.

19. A computing system, comprising:

a plurality of cores;

a plurality of memory controllers coupled to different respective cores; and

processors in the cores configured to;

define striping domains among a plurality of memory controllers of the computing system, to balance workloads within at least one of the defined striping domains;

configure by the system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application to execute on the computing system to balance workloads within the one or more striping domains during execution of the application;

assign an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assignment based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;

receive a memory access request at one of the cores to access data stored at the address; and

determine, in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.