Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques

• US 9,754,072 B1
• Filed: 07/01/2016
• Issued: 09/05/2017
• Est. Priority Date: 11/01/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey S., Raj, Satish, Pribetich, Olivier, Sharma, Karun, Lee, Yinnie, Matsunami, Gary
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US15/201,311
• Time in Patent Office: 431 Days
• Field of Search: 716112
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Claims

1. A computer implemented method for implementing electronic designs using constraint driven techniques, comprising:

using a computing system having at least one processor or at least one processor core to perform a process, the process comprising;

identifying, with a physical implementation rule module including or functioning in conjunction with the at least one processor or the at least one processor core, a set of one or more design rules;

performing data checking and data preparation concerning alignment or positioning of one or more circuit component designs to create design rule-driven data related to an electronic design based at least in part upon the set of one or more design rules; and

generating at least a layout portion that is correct-by-construction with respect to the set of one or more design rules by at least performing structured physical implementation on at least the layout portion of the electronic design based at least in part upon a separate design rule and the design rule-driven data, without performing any design rule checking for the layout portion.

2. The computer implemented method of claim 1, wherein the design rule-drive data includes a set of tracks and design data for one or more boundary pins and one or more instance pins.

3. The computer implemented method of claim 2, wherein the set of tracks is determined or identified from a greater set of grid lines based at least in part upon the set of one or more design rules.

4. The computer implemented method of claim 2, wherein the set of tracks is selected from a greater set of grid lines to intersect or align with a most number of the one or more boundary pins, the one or more instance pins, or a combinations of the one or more boundary pins and the one or more instance pins.

5. The computer implemented method of claim 1, wherein the act of generating the layout portion is performed by using at least the set of tracks in the structured physical implementation.

6. The computer implemented method of claim 1, the process further comprising:

performing additional physical implementation for a second portion of the electronic design not implemented with the structured physical implementation, without regard to the separate design rule;

determining whether the additional physical implementation causes one or more violation of the set of one or more design rules; and

performing a fixing process or an optimization process when the physical implementation is determined to cause the one or more violations.

7. The computer implemented method of claim 6, the act of performing additional physical implementation comprising at least one of:

identifying multiple blocks, cells, or a combination of one or more blocks and one or more cells;

performing intra-block physical implementation for the multiple blocks, cells, or a combination of one or more blocks and one or more cells; and

performing inter-block physical implementation for at least one of the multiple blocks, cells, or a combination of one or more blocks and one or more cells.

8. The computer implemented method of claim 1, the act of performing data checking and data preparation comprising at least one of:

placing or modifying placement of one or more cells on one or more corresponding row sites;

placing or modifying placement of one or more filler cells;

placing or modifying placement of one or more blocks; and

performing pin checking with respect to pin alignment, pin access, or pin escape.

9. The computer implemented method of claim 1, the act of generating the layout portion that is correct-by-construction with respect to the set of one or more design rules by at least performing the structured physical implementation comprising at least one of:

implementing one or more critical nets in the layout portion that is correct-by-construction;

implementing one or more buses in the layout portion that is correct-by-construction;

implementing one or more nets subject to one or more structured constraints in the layout portion that is correct-by-construction; and

locking results of the structured physical implementation from additional changes.

10. The computer implemented method of claim 3, the process further comprising:

iterating through multiple spreading distances in the set of spreading distances based at least in part upon one or more stopping criteria.

15. The article of manufacture of claim 1, the act of generating the layout portion that is correct-by-construction with respect to the set of one or more design rules by at least performing the structured physical implementation comprising at least one of:

implementing one or more critical nets in the correct-by-construction layout;

implementing one or more buses in the correct-by-construction layout;

implementing one or more nets subject to one or more structured constraints in the correct-by-construction layout; and

locking results of the structured physical implementation from additional changes.

11. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing electronic designs using constraint driven techniques, the set of acts comprising:

using a computing system having at least one processor or at least one processor core to perform the set of acts, the set of acts further comprising;

identifying, with a physical implementation rule module including or functioning in conjunction with the at least one processor or the at least one processor core, a set of one or more design rules;

performing data checking and data preparation concerning alignment or positioning of one or more circuit component designs to create design rule-driven data related to an electronic design based at least in part upon the set of one or more design rules; and

generating a layout portion that is correct-by-construction with respect to the set of one or more design rules by at least performing structured physical implementation on at least the layout portion of the electronic design based at least in part upon a separate design rule and the design rule-driven data, without performing any design rule checking for the layout portion.

12. The article of manufacture of claim 11, the set of acts further comprising:

performing additional physical implementation for a second portion of the electronic design not implemented with the structured physical implementation, without regard to the separate design rule;

determining whether the additional physical implementation causes one or more violation of the set of one or more design rules; and

performing a fixing process or an optimization process when the physical implementation is determined to cause the one or more violations.

13. The article of manufacture of claim 12, the act of performing additional physical implementation comprising at least one of:

identifying multiple blocks, cells, or a combination of one or more blocks and one or more cells;

performing intra-block physical implementation for the multiple blocks, cells, or a combination of one or more blocks and one or more cells; and

performing inter-block physical implementation for at least one of the multiple blocks, cells, or a combination of one or more blocks and one or more cells.

14. The article of manufacture of claim 11, the act of performing data checking and data preparation comprising at least one of:

placing or modifying placement of one or more cells on one or more corresponding row sites;

placing or modifying placement of one or more filler cells;

placing or modifying placement of one or more blocks; and

performing pin checking with respect to pin alignment, pin access, or pin escape.

16. A system for implementing electronic designs using constraint driven techniques, comprising:

a computing system having at least one processor or at least one processor core;

a physical implementation rule module including or functioning in conjunction with the at least one processor or the at least one processor core and configured to identify a set of one or more design rules;

the computing system further configured to;

perform data checking and data preparation concerning alignment or positioning of one or more circuit component designs to create design rule-driven data related to an electronic design based at least in part upon the set of one or more design rules; and

generate a layout portion that is correct-by-construction with respect to the set of one or more design rules by at least performing structured physical implementation on at least the layout portion of the electronic design based at least in part upon a separate design rule and the design rule-driven data, without performing any design rule checking for the layout portion.

17. The system of claim 16, wherein the at least one processor or at least one processor core is further to:

perform additional physical implementation for a second portion of the electronic design not implemented with the structured physical implementation, without regard to the separate design rule;

determine whether the additional physical implementation causes one or more violation of the set of one or more design rules; and

perform a fixing process or an optimization process when the physical implementation is determined to cause the one or more violations.

18. The system of claim 17, wherein the at least one processor or at least one processor core that is to perform the additional physical implementation is further to:

identify multiple blocks, cells, or a combination of one or more blocks and one or more cells;

perform intra-block physical implementation for the multiple blocks, cells, or a combination of one or more blocks and one or more cells;

or

perform inter-block physical implementation for at least one of the multiple blocks, cells, or a combination of one or more blocks and one or more cells.

19. The system of claim 16, wherein the at least one processor or at least one processor core that is to perform data checking and data preparation is further to:

place or modify placement of one or more cells on one or more corresponding row sites;

place or modify placement of one or more filler cells;

place or modify placement of one or more blocks;

or

perform pin checking with respect to pin alignment, pin access, or pin escape.

20. The system of claim 16, wherein the at least one processor or at least one processor core that is to generate the layout portion that is correct-by-construction is further to:

implement one or more critical nets in the layout portion;

implement one or more buses in the correct-by-construction layout portion that is correct-by-construction;

implement one or more nets subject to one or more structured constraints in the layout portion that is correct-by-construction;

or

lock results of the structured physical implementation from additional changes.