Memory management system with power source and method of manufacture thereof

• US 9,754,634 B2
• Filed: 11/23/2011
• Issued: 09/05/2017
• Est. Priority Date: 11/23/2011
• Status: Active Grant

• Current Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Original Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Inventors: Shen, Jinying, Frey, Robert Tower, Marino, Kelvin, Brooks, Joshua Harris
• Primary Examiner(s): Alrobaie, Khamdan
• Application Number:
  US13/303,863
• Publication Number:
  US 20130128685A1
• Time in Patent Office: 2,113 Days
• Field of Search: 365226-229, 711161, 711162, 714 14, 714 22
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

Claims

1. A method of manufacture of a memory management system comprising:

mounting a volatile memory device on a dual in-line memory module carrier;

mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device;

mounting an uninterruptible power supply on the dual in-line memory module carrier, the uninterruptible power supply configured to maintain a memory module power when a system power input decays, and wherein the memory module power is reduced by less than 20 millivolts (mV) during a transition time when the memory module power is transitioned from the system power input to a back-up power input, wherein the uninterruptible power supply increases the back-up power input from a first voltage to a second voltage upon detecting a loss of system power from the system power input, and wherein the transition time based on an amount of current drawn by the memory management system; and

mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply, the controller logic integrated circuit configured to copy data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects that the system power input has decayed to a first cross-over level.

2. The method as claimed in claim 1 further comprising providing a voltage switching circuit in the uninterruptible power supply.

3. The method as claimed in claim 1 further comprising providing a control logic unit in the controller logic integrated circuit.

4. The method as claimed in claim 1 further comprising coupling a source transistor between the memory module power and the system power input.

5. The method as claimed in claim 1 wherein providing the back-up power input, in the uninterruptible power supply, includes coupling a secondary power source on the dual in-line memory module carrier.

6. A method of manufacture of a memory management system comprising:

mounting a volatile memory device on the front of dual in-line memory module carrier;

mounting a non-volatile memory on the backside of the dual in-line memory module carrier opposite the volatile memory device;

mounting an uninterruptible power supply on the dual in-line memory module carrier, the uninterruptible power supply configured to maintain a memory module power when a system power input decays including coupling a back-up power input to a secondary power source, and wherein the memory module power is reduced by less than 20 millivolts (mV) during a transition time when the memory module power is transitioned from the system power input to a back-up power input wherein the uninterruptible power supply increases the secondary power source from a first voltage to a second voltage upon detecting a loss of system power from the system power input, and wherein the transition time based on an amount of current drawn by the memory management system; and

mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply, the controller logic integrated circuit configured to copy data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects that the system power input has decayed to a first cross-over level, and enabling a back-up transistor to utilize the secondary power source.

7. The method as claimed in claim 6 further comprising providing a voltage switching circuit, in the uninterruptible power supply, coupled to a source transistor and the back-up transistor.

8. The method as claimed in claim 6 further comprising providing a control logic unit in the controller logic integrated circuit including controlling a first multiplexer between the volatile memory device and the non-volatile memory.

9. The method as claimed in claim 6 further comprising coupling a source transistor between the memory module power and the system power input including providing a voltage switching circuit for disabling the source transistor and enabling the back-up transistor.

10. The method as claimed in claim 6 wherein mounting the uninterruptible power supply includes mounting the uninterruptible power supply having the back-up power input coupled to an anode of a diode and a drain of a transistor.

11. A memory management system comprising:

a dual in-line memory module carrier;

a volatile memory device mounted on the dual in-line memory module carrier;

a non-volatile memory mounted on the dual in-line memory module carrier on a side opposite the volatile memory device;

an uninterruptible power supply on the dual in-line memory module carrier, the uninterruptible power supply configured to maintain a memory module power when a system power input decays, and

wherein the memory module power is reduced by less than 20 millivolts (mV) during a transition time when the memory module power is transitioned from the a system power input to a back-up power input, wherein the uninterruptible power supply increases the secondary power source from a first voltage to a second voltage upon detecting a loss of system power from the system power input, and

wherein the transition time based on an amount of current drawn by the memory management system; and

a controller logic integrated circuit mounted on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply, the controller logic integrated circuit configured to copy data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects that the system power input has decayed to a first cross-over level.

12. The system as claimed in claim 11 further comprising a voltage switching circuit in the uninterruptible power supply.

13. The system as claimed in claim 11 further comprising a control logic unit in the controller logic integrated circuit.

14. The system as claimed in claim 11 further comprising a source transistor coupled between the memory module power and the system power input.

15. The system as claimed in claim 11 wherein the back-up power input, in the uninterruptible power supply, is coupled to a secondary power source on the dual in-line memory module carrier.

16. The system as claimed in claim 11 further comprising:

the back-up power input, on the uninterruptible power supply, coupled to a secondary power source; and

a back-up transistor enabled to utilize the secondary power source.

17. The system as claimed in claim 16 further comprising a voltage switching circuit in the uninterruptible power supply coupled to a source transistor and the back-up transistor.

18. The system as claimed in claim 16 further comprising a control logic unit in the controller logic integrated circuit includes a first multiplexer between the volatile memory device and the non-volatile memory.

19. The system as claimed in claim 16 further comprising a source transistor between the memory module power and the system power input includes a voltage switching circuit for disabling the source transistor and enabling the back-up transistor.

20. The system as claimed in claim 16 wherein the uninterruptible power supply includes the back-up power input coupled to an anode of a diode and a drain of a transistor.