Semiconductor structures having an insulative island structure

• US 9,754,817 B2
• Filed: 06/01/2016
• Issued: 09/05/2017
• Est. Priority Date: 10/25/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kil-Ho, Park, Se-Woong, Kim, Ki-Joon
• Primary Examiner(s): Parker, Allen
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US15/170,043
• Publication Number:
  US 20160329236A1
• Time in Patent Office: 461 Days
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Claims

1. A semiconductor device, comprising:

a gate structure on a substrate;

a first insulating layer on the substrate over the gate structure;

an insulation pattern structure on the first insulating layer above the gate structure, a width of the insulation pattern structure being less than a width of the gate structure and being gradually reduced as a height of the insulation pattern structure becomes higher, wherein the insulation pattern structure includes a first insulation pattern and a second insulation pattern sequentially stacked;

a conductive pattern on the first insulating layer and extending over the insulation pattern structure;

an etch stop layer on the first insulating layer, the etch stop layer partially surrounding a sidewall of the conductive pattern; and

a second insulating layer on the etch stop layer, the second insulating layer partially surrounding the sidewall of the conductive pattern.

4. The semiconductor device of claim 1, further comprising a diffusion barrier between the first insulating layer and the conductive pattern.

5. The semiconductor device of claim 4, wherein the diffusion barrier extends between the insulation pattern structure and the conductive pattern.

6. The semiconductor device of claim 4, wherein the diffusion barrier comprises a metal nitride layer.

2. A semiconductor device, comprising:

a gate structure on a substrate;

a first insulating layer on the substrate over the gate structure;

an insulation pattern structure on the first insulating layer above the gate structure, a width of the insulation pattern structure being less than a width of the gate structure and being gradually reduced as a height of the insulation pattern structure becomes higher, wherein the insulation pattern structure includes a first insulation pattern and a second insulation pattern sequentially stacked;

a conductive pattern on the first insulating layer and extending over the insulation pattern structure;

an etch stop layer on the first insulating layer, the etch stop layer partially surrounding a sidewall of the conductive pattern; and

a second insulating layer on the etch stop layer, the second insulating layer partially surrounding the sidewall of the conductive pattern,

wherein the first insulation pattern includes a material substantially the same as that of the etch stop layer, and wherein the second insulation pattern includes a material substantially the same as that of the second insulating layer.

3. The semiconductor device of claim 2, wherein the first insulation pattern includes silicon nitride, and wherein the second insulation pattern includes silicon oxide.

7. A semiconductor device, comprising:

a gate structure on a substrate;

a first insulating layer on the substrate over the gate structure;

an insulation pattern structure on the first insulating layer above the gate structure, a width of the insulation pattern structure being less than a width of the gate structure and being gradually reduced as a height of the insulation pattern structure becomes higher, wherein the insulation pattern structure includes a first insulation pattern and a second insulation pattern sequentially stacked;

a conductive pattern on the first insulating layer and extending over the insulation pattern structure;

an etch stop layer on the first insulating layer, the etch stop layer partially surrounding a sidewall of the conductive pattern; and

a second insulating layer on the etch stop layer, the second insulating layer partially surrounding the sidewall of the conductive pattern,

further comprising a diffusion barrier between the first insulating layer and the conductive pattern, wherein the diffusion barrier contacts sidewalls of the first insulation pattern, the second insulation pattern, the etch stop layer and the second insulating layer.