Substrate structure, electronic package and method for fabricating the electronic package

• US 9,754,868 B2
• Filed: 03/14/2016
• Issued: 09/05/2017
• Est. Priority Date: 12/31/2015
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Inventors: Chiang, Ching-Wen, Wang, Hsin-Chih, Shih, Chih-Yuan, Chen, Shih-Ching
• Primary Examiner(s): Le, Thao P
• Application Number:
  US15/069,387
• Publication Number:
  US 20170194238A1
• Time in Patent Office: 540 Days
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates

Abstract

A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.

Claims

1. An electronic package, comprising:

a substrate body having a first surface and a second surface opposite to the first surface;

a plurality of conductive posts disposed on and protruding from the first surface of the substrate body and electrically connected to the substrate body, wherein a side of each of the conductive posts has an insulating layer, and any two adjacent ones of the insulating layers of the conductive posts have an air gap formed therebetween;

at least an electronic element disposed on the second surface of the substrate body and electrically connected to the substrate body; and

an encapsulant formed on the second surface of the substrate body and encapsulating the electronic element.

2. The electronic package of claim 1, wherein each of the conductive posts has a length to width ratio in a range of from 1 to 5.

3. The electronic package of claim 1, further comprising a plurality of conductive elements formed on the conductive posts.

4. A substrate structure, comprising:

a substrate body having a first surface and a second surface opposite to the first surface;

a plurality of conductive posts disposed on and protruding from the first surface of the substrate body and electrically connected to the substrate body, wherein a side of each of the conductive posts has an insulating layer, and any two adjacent ones of the insulating layers of the conductive posts have an air gap formed therebetween.

5. The substrate structure of claim 4, wherein each of the conductive posts has a length to width ratio in a range of from 1 to 5.

6. The substrate structure of claim 4, further comprising a plurality of conductive elements disposed on the conductive posts.