3D integration using Al—Ge eutectic bond interconnect

• US 9,754,922 B2
• Filed: 02/10/2016
• Issued: 09/05/2017
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Smeys, Peter, Maghsoudnia, Mozafar
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US15/040,823
• Publication Number:
  US 20160233197A1
• Time in Patent Office: 573 Days
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/16111 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16502 comprising an eutectic alloy
• CPC Class Codes: H01L 2224/16506 comprising an eutectic alloy
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81906 Specific sequence of method steps
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.

Claims

1. An apparatus comprising:

a first CMOS wafer;

a second CMOS wafer including a depression within a surface of the second CMOS wafer, wherein the depression includes an aluminum surface; and

a eutectic bond connecting the first CMOS wafer to the second CMOS wafer, wherein

the eutectic bond includes aluminum and germanium,

the eutectic bond has a melting point which is lower than the melting point of aluminum and the melting point of germanium, and

the eutectic bond includes the aluminum surface.

2. The apparatus of claim 1, wherein

the first CMOS wafer includes an aluminum standoff and a germanium layer on the first standoff, and

the eutectic bond includes the aluminum standoff.

3. The apparatus of claim 1, wherein

the first CMOS wafer includes a germanium standoff, and

the eutectic bond includes the germanium standoff.

4. The apparatus of claim 1, further comprising a plurality of eutectic bonds connecting the first CMOS wafer to the second CMOS wafer.

5. The apparatus of claim 1, further comprising a standoff height between the first CMOS wafer and the second CMOS wafer, wherein the standoff height is between 0 and 2000 Å

.

6. An apparatus comprising:

a first feature on a first CMOS wafer, wherein the first feature is a standoff with a height;

a second feature on a second CMOS wafer, wherein the second feature is a depression with a depth, wherein the height is greater than the depth; and

a eutectic bond connecting the first feature to the second feature, wherein the eutectic bond has a melting point which is lower than the melting point of the first feature and the melting point of the second feature.

7. The apparatus of claim 6, wherein the first feature includes aluminum.

8. The apparatus of claim 6, wherein the second feature includes germanium.

9. The apparatus of claim 6, wherein the eutectic bond includes portions of the first feature and portions of the second feature melted together.

10. The apparatus of claim 6, wherein the first feature includes a height less than 500 Å

.

11. An apparatus comprising:

a first CMOS wafer;

a second CMOS wafer including a depression within a surface of the second CMOS wafer, wherein the depression includes a germanium surface; and

a eutectic bond connecting the first CMOS wafer to the second CMOS wafer, wherein

the eutectic bond includes aluminum and germanium,

the eutectic bond includes a melting point which is lower than the melting point of aluminum and the melting point of germanium; and

the eutectic bond includes the germanium surface.

12. The apparatus of claim 11, further comprising a plurality of eutectic bonds connecting the first CMOS wafer to the second CMOS wafer.

13. The apparatus of claim 11, further comprising a standoff height between the first CMOS wafer and the second CMOS wafer, wherein the standoff height is between 0 and 2000 Å

.

14. An apparatus comprising:

a first feature on a first CMOS wafer;

a second feature on a second CMOS wafer; and

a eutectic bond connecting the first feature to the second feature, wherein

the eutectic bond includes a melting point which is lower than the melting point of the first feature and the melting point of the second feature, and

a width of the eutectic bond is narrower than a width of the second feature.

15. The apparatus of claim 14, wherein the first feature includes aluminum.

16. The apparatus of claim 14, wherein the second feature includes germanium.

17. The apparatus of claim 14, wherein the eutectic bond includes portions of the first feature and portions of the second feature melted together.

18. The apparatus of claim 14, wherein the first feature includes a height less than 500 Å

.