Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)

• US 9,754,923 B1
• Filed: 05/09/2016
• Issued: 09/05/2017
• Est. Priority Date: 05/09/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xie, Jing, Samadi, Kambiz, Kamal, Pratyush, Du, Yang, Jaffari, Javid
• Primary Examiner(s): Stark, Jarrett
• Application Number:
  US15/149,646
• Time in Patent Office: 484 Days
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory

Abstract

Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

Claims

1. A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:

a first tier;

a second tier adjacent to the first tier in a face-to-face arrangement; and

an inter-tier via providing electrical connections between the first tier and the second tier;

the first tier comprising a logic circuit and an absence of power gating circuits; and

the second tier comprising a power gating circuit connected to the logic circuit through the inter-tier via, wherein the power gating circuit is configured to provide power selectively to the logic circuit.

2. The monolithic 3DIC of claim 1, wherein the logic circuit comprises one of a computational circuit, an analog process circuit, a digital process circuit, and a memory circuit.

3. The monolithic 3DIC of claim 1, wherein the second tier further comprises a voltage source interface, wherein the voltage source interface is electrically connected to the power gating circuit.

4. The monolithic 3DIC of claim 1, wherein technology nodes of the first tier are heterogeneous relative to technology nodes of the second tier.

5. The monolithic 3DIC of claim 1, wherein technology nodes of the first tier and technology nodes of the second tier are homogeneous.

6. The monolithic 3DIC of claim 1, wherein the second tier comprises a plurality of metal layers proximate a face of the second tier and a backside metal layer proximate an outer surface of the 3DIC and wherein the backside metal layer comprises a voltage source bump interface.

7. The monolithic 3DIC of claim 6, wherein the backside metal layer couples to the power gating circuit using no more than one metal layer of the plurality of metal layers in the second tier.

8. The monolithic 3DIC of claim 3, wherein the voltage source interface comprises an external voltage source interface.

9. The monolithic 3DIC of claim 8, wherein the power gating circuit comprises a PMOS-based element.

10. The monolithic 3DIC of claim 3, wherein the voltage source interface comprises a ground node interface.

11. The monolithic 3DIC of claim 10, wherein the power gating circuit comprises an NMOS-based element.

12. The monolithic 3DIC of claim 1, wherein the first tier comprises at least one non-logic circuit.

13. The monolithic 3DIC of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a smart phone;

a tablet;

a phablet;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player;

a portable digital video player; and

an automobile.

15. The monolithic 3DIC of claim 3, wherein the second tier further comprises a plurality of metal layers.

16. The monolithic 3DIC of claim 15, wherein the power gating circuit is connected to the voltage source interface through only one metal layer of the plurality of metal layers.

14. A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:

a first tier;

a second tier adjacent to the first tier in a face-to-face arrangement; and

a means for providing electrical connections between the first tier and the second tier;

the first tier comprising a logic circuit and an absence of power gating circuits; and

the second tier comprising a means for power gating connected to the logic circuit through an inter-tier via, wherein the means for power gating is configured to provide power selectively to the logic circuit.