Raised metal semiconductor alloy for self-aligned middle-of-line contact

• US 9,754,935 B2
• Filed: 08/07/2014
• Issued: 09/05/2017
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lavoie, Christian, Leobandung, Effendi
• Primary Examiner(s): Pizarro Crespo, Marcos D
• Assistant Examiner(s): GARCES, NELSON Y
• Application Number:
  US14/453,751
• Publication Number:
  US 20160043075A1
• Time in Patent Office: 1,125 Days
• Field of Search: 257259-269
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.

Claims

1. A semiconductor structure comprising:

a plurality of functional gate structures located over at least one active region of a substrate, each of the plurality of functional gate structures comprises a stack of a gate dielectric, a gate electrode, and a gate cap;

a plurality of planar source/drain regions, each of the plurality of planar source/drain regions positioned in a portion of the at least one active region located between adjacent functional gate structures of the plurality of functional gate structures;

a plurality of raised source/drain regions, each of the plurality of raised source/drain regions overlying a corresponding planar source/drain region of the plurality of planar source/drain regions and having a top surface located below a top surface of the gate electrode;

a plurality of metal semiconductor alloy regions, each of the plurality of metal semiconductor alloy regions overlying a corresponding raised source/drain region of the plurality of raised source/drain regions and having a top surface substantially coplanar with topmost surfaces of the plurality of functional gate structures; and

interlevel dielectric (ILD) layer portions located on the substrate and laterally surrounding the plurality of raised source/drain regions and lower portions of the plurality of metal semiconductor alloy regions, wherein top surfaces of the ILD layer portions are located below the top surface of each of the plurality of metal semiconductor alloy regions.

2. The semiconductor structure of claim 1, wherein the plurality of raise source/drain regions comprises a silicon-containing semiconductor material or a germanium-containing semiconductor material.

3. The semiconductor structure of claim 1, wherein the plurality of metal semiconductor alloy regions comprises a metal silicide or a metal germicide.

4. The semiconductor structure of claim 3, wherein the metal silicide comprises platinum silicide, palladium silicide, or lanthanum silicide, and wherein the metal germicide comprises platinum germicide, palladium germicide, or lanthanum germicide.

5. The semiconductor structure of claim 1, further comprising a plurality of source/drain contact structures extending through at least one contact level dielectric layer and in contact with the plurality of metal semiconductor alloy regions, and a plurality of gate contact structures extending through the at least one contact level dielectric layer and the gate cap in each of the plurality of functional gate structures and in contact with the gate electrode in each of the plurality of functional gate structures, wherein a bottommost surface of the at least one contact level dielectric layer is in contact with top surfaces of the ILD layer portions.

6. The semiconductor structure of claim 1, wherein the ILD layer portions comprise a doped silicate glass, an undoped silicate glass, an organosilicate glass, a porous dielectric material, or amorphous carbon.

7. The semiconductor structure of claim 5, wherein the at least one contact level dielectric layer comprises, from bottom to top, a first contact level dielectric layer, an etch stop layer, and a second contact level dielectric layer.

8. The semiconductor structure of claim 7, wherein each of the first contact level dielectric layer and the second contact level dielectric layer comprises silicon oxide, and the etch stop layer comprises silicon nitride.

9. The semiconductor structure of claim 5, wherein the at least one contact level dielectric layer laterally surrounds upper portions of the plurality of metal semiconductor alloy regions.

10. The semiconductor structure of claim 1, wherein the plurality of raised source/drain regions laterally surrounds lower portions of the plurality of the functional gate structure.

11. The semiconductor structure of claim 1, further comprising a gate spacer present on each sidewall of the plurality of functional gate structures.