Non-volatile programmable memory cell and array for programmable logic array
First Claim
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1. A non-volatile programmable memory cell comprising:
- a non-volatile MOS transistor formed in a first semiconductor region and coupled between a first power supply potential and an output node;
a volatile MOS transistor formed in a second semiconductor region and coupled between the output node and a second power supply potential; and
a volatile MOS switch transistor formed in a third semiconductor region electrically isolated from the first semiconductor region, the volatile MOS switch transistor having a gate couple to the output nodewherein the non-volatile MOS transistor includes a gate and a diffused region having first and second ends, the diffused region including a first contact at the first end, a second contact at the second end, and a channel region between the first and second ends and below the gate, the diffused region having a first width at the first end and a second width at the second end, wherein the first and second widths are wider than a width of the channel region.
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Abstract
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
30 Citations
20 Claims
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1. A non-volatile programmable memory cell comprising:
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a non-volatile MOS transistor formed in a first semiconductor region and coupled between a first power supply potential and an output node; a volatile MOS transistor formed in a second semiconductor region and coupled between the output node and a second power supply potential; and a volatile MOS switch transistor formed in a third semiconductor region electrically isolated from the first semiconductor region, the volatile MOS switch transistor having a gate couple to the output node wherein the non-volatile MOS transistor includes a gate and a diffused region having first and second ends, the diffused region including a first contact at the first end, a second contact at the second end, and a channel region between the first and second ends and below the gate, the diffused region having a first width at the first end and a second width at the second end, wherein the first and second widths are wider than a width of the channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A non-volatile programmable memory cell formed in a p-type semiconductor substrate and comprising:
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a non-volatile n-channel MOS transistor formed in a first p-type semiconductor region and coupled between a first power supply potential and an output node; a volatile p-channel MOS transistor formed in an n-type semiconductor region and coupled between the output node and a second power supply potential; and a volatile n-channel MOS switch transistor formed in a second p-type semiconductor region and coupled to the output node; wherein; the non-volatile MOS transistor includes a gate and a diffused region having a first contact at a first end thereof, a second contact at a second end thereof, and a channel region between the first and second ends and below the gate, the diffused region having a first width at the first end and a second width at the second end, wherein the first and second widths are wider than a width of the channel region; and the first and second p-type semiconductor regions are electrically isolated from one another. - View Dependent Claims (14, 15, 16)
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17. A non-volatile programmable memory cell formed in a p-type semiconductor substrate and comprising:
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a volatile n-channel MOS transistor formed in a first p-type semiconductor region and coupled between a first power supply potential and an output node; a non-volatile p-channel MOS transistor formed in an n-type semiconductor region and coupled between the output node and a second power supply potential; and a volatile n-channel MOS switch transistor formed in a second p-type semiconductor region and coupled to the output node; wherein; the non-volatile p-channel MOS transistor includes a gate and a diffused region having first and second ends, the diffused region including a first contact at the first end, a second contact at the second end, and a channel region between the first and second ends and below the gate, the diffused region having a first width at the first end and a second width at the second end, wherein the first and second widths are wider than a width of the channel region; and the first and second p-type semiconductor regions are electrically isolated from one another. - View Dependent Claims (18, 19, 20)
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Specification