Semiconductor memory device including power decoupling capacitor

• US 9,754,960 B2
• Filed: 01/19/2016
• Issued: 09/05/2017
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Jeon, Jae Eun
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US15/000,635
• Publication Number:
  US 20170053932A1
• Time in Patent Office: 595 Days
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. The power decoupling capacitor circuit includes conductive lines which are alternately stacked on top of one another, a plurality of semiconductor pillars configured to pass through the conductive lines, a horizontal connector configured to connect the semiconductor pillars to each other, and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.

Claims

1. A semiconductor memory device comprising:

a memory cell array having a multilayer stacked structure; and

a peripheral circuit configured to drive the memory cell array,

wherein the peripheral circuit comprises a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit,

wherein the power decoupling capacitor circuit comprises;

conductive lines alternately stacked on top of one another;

a plurality of semiconductor pillars configured to pass through the conductive lines;

a horizontal connector configured to connect the semiconductor pillars to each other; and

a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.

2. The semiconductor memory device according to claim 1, wherein a contact plug to which a power voltage is applied is formed on an upper portion of the vertical connector, and another contact plug to which a ground voltage is applied is formed on an upper portion of the horizontal connector.

3. The semiconductor memory device according to claim 1, wherein the vertical connector is configured to connect the conductive lines to each other in a vertical direction.

4. The semiconductor memory device according to claim 1, wherein each of the semiconductor pillars comprises a capacitor string including a plurality of transistors, and

the conductive lines are connected to respective gate electrodes of the plurality of transistors.

5. The semiconductor memory device according to claim 1, wherein each of the semiconductor pillars is brought into contact with at least one of the conductive lines.

6. The semiconductor memory device according to claim 1, wherein each of the semiconductor pillars comprises:

an internal material including an insulation material;

an intermediate layer; and

a surface layer,

wherein the surface layer comprises a tunneling insulation film, a charge storage film, and a blocking insulation film which are successively disposed from the intermediate layer.

7. The semiconductor memory device according to claim 1, wherein each of the conductive lines is made of conductive material, wherein the conductive material is formed of polysilicon.

8. The semiconductor memory device according to claim 1, further comprising

an insulation material formed between the conductive lines.

9. The semiconductor memory device according to claim 8, wherein the insulation material is silicon oxide.

10. A semiconductor memory device comprising:

a semiconductor substrate including a cell region and a peripheral circuit region;

conductive lines stacked on top of one another in the cell region and the peripheral circuit region;

a plurality of semiconductor pillars configured to pass through the conductive lines;

a horizontal connector configured to connect the semiconductor pillars that are disposed in the peripheral circuit region; and

a vertical connector configured to pass through the conductive lines that are disposed in the peripheral circuit region, the vertical connector being insulated from the horizontal connector,

wherein each of the semiconductor pillars that are disposed in the peripheral circuit region comprises a capacitor string including a plurality of transistors, and

the conductive lines are connected to respective gate electrodes of the plurality of transistors.

11. The semiconductor memory device according to claim 10, wherein a contact plug to which a power voltage is applied is formed on an upper portion of the vertical connector, and another contact plug to which a ground voltage is applied is formed on an upper portion of the horizontal connector.

12. The semiconductor memory device according to claim 10, wherein the vertical connector is configured to connect the conductive lines to each other in a vertical direction.

13. The semiconductor memory device according to claim 10, wherein the semiconductor pillars is brought into contact with at least one of the conductive lines.

14. The semiconductor memory device according to claim 10, wherein each of the semiconductor pillars comprises:

an internal material including an insulation material;

an intermediate layer; and

a surface layer,

wherein the surface layer comprises a tunneling insulation film, a charge storage film, and a blocking insulation film which are successively disposed from the intermediate layer.

15. The semiconductor memory device according to claim 10, wherein each of the conductive lines is made of conductive material, wherein the conductive material is formed of polysilicon.

16. The semiconductor memory device according to claim 10, further comprising an insulation material formed between the conductive lines.

17. The semiconductor memory device according to claim 16, wherein the insulation material is silicon oxide.