Display device, thin film transistor, array substrate and manufacturing method thereof

• US 9,754,979 B2
• Filed: 09/29/2012
• Issued: 09/05/2017
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Ning, Ce, Zhang, Xuehui, Yang, Jing
• Primary Examiner(s): Dang, Trung Q
• Assistant Examiner(s): Haider, Wasiul
• Application Number:
  US13/703,483
• Publication Number:
  US 20140091331A1
• Time in Patent Office: 1,802 Days
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

The embodiments of the invention provide a display device, a thin film transistor, an array substrate and a manufacturing method thereof. The manufacturing method comprises: step A, forming patterns of a source electrode, a drain electrode, a data line and a pixel electrode; step B, forming an active layer and agate insulating layer in order, and forming a via hole in the gate insulating layer for connecting the data line and an external circuit; and step C, forming patterns of a gate electrode, a gate line and a common electrode line, or forming a pattern of a gate electrode, a gate line and a common electrode.

Claims

1. A manufacturing method of array substrate comprising:

step A, forming patterns of a source electrode, a drain electrode, a data line and a pixel electrode on a substrate by a first patterning process, wherein the source electrode, the drain electrode, the data line and the pixel electrode are formed of a same layer of transparent conductive material, the drain electrode and the pixel electrode are integrally formed, with each other, of the same transparent conductive material, and etching a portion of the transparent conductive material such that a thickness of the pixel electrode is less than a thickness of the source electrode and the drain electrode;

step B, forming an active layer and a gate insulating layer in order on the patterns of the source electrode, the drain electrode, the data line and the pixel electrode, and patterning the gate insulating layer by a second patterning process; and

step C, forming patterns of a gate electrode, a gate line and a common electrode line on the gate insulating layer by a third patterning process, wherein the common electrode line and the pixel electrode are partially overlapped to form a storage capacitor, or

forming patterns of a gate electrode, a gate line and a common electrode on the gate insulating layer by a third patterning process, wherein the common electrode is adapted to generate a driving electric field along with the pixel electrode.

2. The manufacturing method according to claim 1, wherein:

the step A comprises;

forming a first layer of transparent conducting thin film on a substrate, and forming the patterns of the source electrode, the drain electrode, the data line and the pixel electrode by the first patterning process;

the step C comprises;

forming a second layer of transparent conducting thin film, and forming the patterns of the gate electrode, the gate line and the common electrode line by the third patterning process, or forming the patterns of the gate electrode, the gate line and the common electrode by the third patterning process.

3. The manufacturing method according to claim 2, wherein forming the patterns of the source electrode, the drain electrode, the data line and the pixel electrode by the patterning process comprises:

forming a layer of photoresist on the first layer of transparent conducting thin film;

exposing the photoresist with a double-tone mask plate to obtain a latent image for forming a non-retained region of photoresist, a partially-retained region of photoresist and a retained region of photoresist;

developing;

etching off the first layer of transparent conducting thin film in the non-retained region of photoresist to form the patterns of the source electrode, the drain electrode and the data line;

removing the photoresist in the partially-retained region of photoresist by an aching process and keeping the photoresist in the retained region of photoresist;

etching the first layer of transparent conducting thin film in the partially-retained region of photoresist to make this portion of the first layer of transparent conducting thin film to become thinner so as to form the pattern of the pixel electrode; and

removing remaining photoresist.

4. The manufacturing method according to claim 2, wherein said patterning the gate insulation layer by a second patterning process comprises:

forming a layer of photoresist on the gate insulating layer;

exposing the photoresist using a mask plate to obtain a latent image for forming a retained region of photoresist and a non-retained region of photoresist;

developing;

etching off the gate insulating layer and active layer in the non-retained region of photoresist; and

removing remaining photoresist.

5. The manufacturing method according to claim 2, wherein forming the patterns of the gate electrode, the gate line and the common electrode line by the patterning process comprises:

forming a layer of photoresist on the second layer of transparent conducting thin film;

exposing the photoresist using a mask plate to obtain a latent image for forming a retained region of photoresist and a non-retained region of photoresist;

developing;

etching off the second layer of transparent conducting thin film in the non-retained region of photoresist to form the patterns of the gate electrode, the gate line and the common electrode line; and

removing remaining photoresist.

6. The manufacturing method according to claim 2, wherein forming the patterns of the gate electrode, the gate line and the common electrode by a third patterning process comprises:

forming a layer of photoresist on the second layer of transparent conducting thin film;

exposing the photoresist using a mask plate to obtain a latent image for forming a retained region of photoresist and a non-retained region of photoresist;

developing;

etching the second layer of transparent conducting thin film in the non-retained region of photoresist to form the patterns of the gate electrode, the gate line and the common electrode; and

removing remaining photoresist.

7. The manufacturing method according to claim 1, wherein:

the common electrode comprises slits.

8. The manufacturing method according to claim 1, wherein:

the active layer comprises an oxide semiconductor material.

15. The manufacturing method according to claim 6, wherein:

the common electrode comprises slits.

9. An array substrate comprising:

a source electrode, a drain electrode, a data line and a pixel electrode formed on a base substrate, a channel region being defined between the source electrode and the drain electrode, the drain electrode and the pixel electrode being electrically connected with each other, and the data line being connected to an external circuit, wherein the source electrode, the drain electrode, the data line and the pixel electrode are formed of a same layer of transparent conductive material, the drain electrode and the pixel electrode are integrally formed, with each other, of the same transparent conductive material, and a thickness of the pixel electrode is less than a thickness of the source electrode and the drain electrode, wherein a thicker portion of the source electrode or drain electrode is made of the transparent conductive material only;

an active layer formed on the source electrode, the drain electrode, the data line and the pixel electrode;

a gate insulating layer formed on the active layer;

a gate electrode, a gate line and a common electrode line formed on the gate insulating layer, wherein the common electrode line and the pixel electrode are partially overlapped to form a storage capacitor, or a gate electrode, a gate line and a common electrode formed on the gate insulating layer, wherein the common electrode is adapted to generate a driving electric field along with the pixel electrode.

10. The array substrate according to claim 9, wherein:

the active layer comprises an oxide material.

11. The array substrate according to claim 9, wherein:

the common electrode comprises slits.

12. The array substrate according to claim 9, wherein the source electrode, the drain electrode, the data line and the pixel electrode are formed from a same transparent conducting thin film.

13. A display device comprising the array substrate according to claim 9.

14. The display device according to claim 13, wherein the display device is a liquid crystal display device or an organic light emitting diode (OLEO) device.

16. The array substrate according to claim 10, wherein:

the common electrode comprises slits.