Semiconductor device and method of manufacturing thereof

• US 9,754,991 B2
• Filed: 09/20/2016
• Issued: 09/05/2017
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Kasai, Hiroki
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US15/270,101
• Publication Number:
  US 20170092686A1
• Time in Patent Office: 350 Days
• Field of Search: 257347
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14659 Direct radiation imagers structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H10K 39/36 Devices specially adapted for detecting X-ray radiation

Abstract

A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface and having a sensor therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein. The second semiconductor layer is formed at a same side of the primary surface of the first semiconductor layer. The device further includes an insulating layer formed between the first semiconductor layer and the second semiconductor layer. The insulating layer is disposed on the primary surface of the first semiconductor layer and surrounds the circuit element, and includes a charge-attracting semiconductor pattern of the first conductivity type that is disposed near the circuit element so as to attract electrical charges generated in the insulating layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface on an opposite side thereof, and having a sensor therein;

a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at said one side of the primary surface of the first semiconductor layer;

an insulating layer formed between the first semiconductor layer and the second semiconductor layer, the insulating layer being disposed on the primary surface of the first semiconductor layer and surrounding the circuit element, the insulating layer including a charge-attracting semiconductor pattern of the first conductivity type that is disposed in relation to the circuit element so as to attract electrical charges generated in the insulating layer.

2. The semiconductor device according to claim 1, wherein

the circuit element includes a field-effect transistor, and

the charge-attracting semiconductor pattern has two regions, the two regions being disposed in relation to one and another of ends of the field-effect transistor in a gate width direction, respectively, and extending in a gate length direction in a plan view, so as to attract the electrical charges.

3. The semiconductor device according to claim 1, wherein

the circuit element includes a field-effect transistor, and

the charge-attracting semiconductor layer surrounds the field-effect transistor in a plan view, and is disposed in relation to the field-effect transistor so as to attract the electrical charges.

4. The semiconductor device according to claim 1 further comprising a fixed potential region of the second conductivity type that is formed in the first semiconductor layer so as to cover an area in which the charge-attracting semiconductor pattern is formed in a plan view, the fixed potential region including a contact region.

5. The semiconductor device according to claim 1, further comprising:

an intermediate semiconductor layer formed in the insulating layer between the first semiconductor layer and the second semiconductor layer; and

a fixed potential region of the first conductivity type that is formed in the intermediate semiconductor layer so as to cover an area in which the charge-attracting semiconductor pattern is formed in a plan view, the fixed potential region including a contact region.

6. The semiconductor device according to claim 4, further comprising first, second, and third power sources, a first voltage of the first power source being greater than a second voltage of the second power source and a third voltage of the third power source, the second voltage being equal to or greater than the third voltage, wherein

the circuit element includes a field-effect transistor;

the first conductivity type is n-type and the second conductivity type is p type;

the sensor includes;

a p-type semiconductor region and an n-type semiconductor region formed on the one side of the primary surface of the first semiconductor layer, and

a rear electrode disposed on the other side of the secondary surface of the first semiconductor layer, wherein

the n-type semiconductor region and the rear electrode are connected to a positive electrode of the first power source, and

the p-type semiconductor region is connected to a negative electrode of the first power source;

source and drain regions of the field-effect transistor are connected to the second power source via first electrodes; and

the charge-attracting semiconductor pattern and the contact region of the fixed potential region are connected to the third power source via second electrodes.

7. The semiconductor device according to claim 1, wherein the charge-attracting semiconductor pattern is made of polysilicon.

8. A manufacturing method of a semiconductor device, comprising:

preparing a semiconductor substrate that includes a first semiconductor layer of a first conductivity type, a first insulating layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the first insulating layer;

forming, in a portion of the second semiconductor layer, an active region of the second conductivity type so as to be surrounded by a second insulating layer, the second insulating layer being integrally formed with the first insulating layer; and

forming a charge-attracting semiconductor pattern in the first insulating layer adjacent to the active region for attracting electric charges to be generated in the first insulating layer or the second insulating layer during use of the device.

9. The manufacturing method of a semiconductor device according to claim 8, further comprising forming a fixed potential region of the second conductivity type in the first semiconductor layer so as to cover an area in which the charge-attracting semiconductor pattern is formed in a plan view.

10. A manufacturing method of a semiconductor device, comprising:

preparing a semiconductor substrate that includes

a first semiconductor layer of a first conductivity type,

a first insulating layer formed on the first semiconductor layer,

an intermediate semiconductor layer of the first conductivity type formed on the first insulating layer,

a second insulating layer formed on the intermediate semiconductor layer, and

a second semiconductor layer formed on the second insulating layer;

forming, in a portion of the second semiconductor layer, an active region of the second conductivity type so as to be surrounded by a third insulating layer, the third insulating layer being integrally formed with the second insulating layer; and

forming a charge-attracting semiconductor pattern in the second insulating layer adjacent to the active region to attract electric charges generated in the second insulating layer or the third insulating layer.

11. The manufacturing method of a semiconductor device according to claim 10 further comprising forming a fixed potential region of the first conductivity type in the intermediate semiconductor layer so as to cover an area in which the charge-attracting semiconductor pattern is formed in a plan view.