Co-integration of silicon and silicon-germanium channels for nanosheet devices

• US 9,755,017 B1
• Filed: 03/01/2016
• Issued: 09/05/2017
• Est. Priority Date: 03/01/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guillorn, Michael A., Lauer, Isaac, Loubet, Nicolas J.
• Primary Examiner(s): Nguyen, Tram H
• Application Number:
  US15/057,439
• Publication Number:
  US 20170256610A1
• Time in Patent Office: 553 Days
• Field of Search: 257190, 257E21409, 977755, 977924, 438270
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

Claims

1. A method for forming nanosheet semiconductor devices, comprising:

forming a first nanosheet stack in a first device region comprising layers of a first channel material and layers of a sacrificial material;

forming a second nanosheet stack in a second device region comprising layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material;

etching away the sacrificial material using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner, wherein the liner protects the second channel material from the wet etch; and

forming gate stacks over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

2. The method of claim 1, wherein the first channel material is silicon and the second channel material is silicon germanium having a germanium concentration of about 30%.

3. The method of claim 2, wherein the liner is silicon.

4. The method of claim 1, wherein the sacrificial material is silicon germanium having a germanium concentration of about 50%.

5. The method of claim 1, further comprising:

forming a dummy gate stack over channel regions of the first and second nanosheet stacks;

depositing a passivating insulator layer around the dummy gate stacks; and

etching away the dummy gate stacks prior to etching away the sacrificial material.

6. The method of claim 5, further comprising etching away material of the first and second nanosheet stacks that is not covered by the dummy gate stacks to form first and second channel region stacks.

7. The method of claim 6, further comprising forming a vertical liner on sidewalls of the second channel region stack, wherein the vertical liner protects the second channel material from lateral etching.

8. The method of claim 6, further comprising etching trenches in the first and second nanosheet stacks to separate each nanosheet stack into a first and second plurality of nanosheet fins.

9. The method of claim 8, further comprising depositing source and drain regions at respective ends of each nanosheet fins, wherein source and drain regions of the first plurality of nanosheet fins are n-type doped and wherein the source and drain regions of the second plurality of nanosheet fins are p-type doped.

10. A method for forming nanosheet semiconductor devices, comprising:

forming a first nanosheet stack in a first device region comprising alternating layers of silicon and layers silicon germanium having a germanium concentration of about 50%;

forming a second nanosheet stack in a second device region comprising layers of silicon germanium having a germanium concentration of about 30%, layers of silicon germanium having a germanium concentration of about 50%, and a silicon liner formed around the layers of silicon germanium having a germanium concentration of about 30%;

etching away the sacrificial material with a wet etch that is selective to the silicon germanium layers and does not affect the silicon layers or the silicon liner, wherein the silicon liner protects the layers silicon germanium having a germanium concentration of about 30% from the etch; and

forming gate stacks over and around the layers of silicon and the layers of silicon germanium having a germanium concentration of about 30% to form respective first and second semiconductor devices in the first and second device regions.

11. The method of claim 10, further comprising:

forming a dummy gate stack over channel regions of the first and second nanosheet stacks;

depositing a passivating insulator layer around the dummy gate stacks; and

etching away the dummy gate stacks prior to etching away the sacrificial material.

12. The method of claim 11, further comprising etching away material of the first and second nanosheet stacks that is not covered by the dummy gate stacks to form first and second channel region stacks.

13. The method of claim 12, further comprising forming a vertical silicon liner on sidewalls of the second channel region stack, wherein the vertical silicon liner protects the layers of silicon germanium having a germanium concentration of about 30% from lateral etching.

14. An integrated chip, comprising:

a first semiconductor device comprising a plurality of first nanosheet channel layers of a first semiconductor material;

a second semiconductor device comprising a plurality of second nanosheet channel layers of a second semiconductor material and a liner formed around the second nanosheet channel layers;

gate stacks formed over and around the first and second nanosheet channel layers respectively; and

a vertical liner on sidewalls of the gate stack that is over the second nanosheet channel layers.

15. The integrated chip of claim 14, wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium having a germanium concentration of about 30%.

16. The integrated chip of claim 15, wherein the liner is silicon.

17. The integrated chip of claim 14, further comprising first and second source/drain regions at opposite ends of the respective first and second nanosheet channel layers.

18. The integrated chip of claim 17, wherein the source and drain regions of the first semiconductor device are n-type doped and wherein the source and drain regions of the second semiconductor device are p-type doped.