Semiconductor device and method for manufacturing the same

• US 9,755,028 B2
• Filed: 07/16/2015
• Issued: 09/05/2017
• Est. Priority Date: 12/05/2014
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Super Group Semiconductor Co., Ltd.
• Inventors: Lee, Yuan-Ming, Yeh, Chun-Ying
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US14/801,817
• Publication Number:
  US 20160163805A1
• Time in Patent Office: 782 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an epitaxial layer on a substrate;

forming a trench in the epitaxial layer;

forming a first dielectric layer and a shield layer in the trench, wherein the shield layer is embedded within the first dielectric layer;

forming a spacer layer in the trench and on the first dielectric layer, wherein the spacer layer directly contacts the epitaxial layer, the spacer layer is made of PolySilicon, the dopant ion concentration of the spacer layer is greater than the dopant ion concentration of the epitaxial layer, and the first dielectric layer electrically isolates the spacer layer and the shield layer; and

forming a second dielectric layer and a gate in the trench and on the spacer layer, and forming a source in the epitaxial layer surrounding the trench, wherein the spacer layer separates the first dielectric layer and the second dielectric layer, the gate is embedded within the second dielectric layer, and the source surrounds the gate.

2. The method of claim 1, wherein in the operation of forming the first dielectric layer and the shield layer, a barrier layer is formed between the shield layer and the spacer layer.

3. The method of claim 2, wherein the barrier layer is made of silicon nitride.

4. The method of claim 1, wherein in the operation of forming the first dielectric layer and the shield layer, a barrier layer is formed between the shield layer and the epitaxial layer.

5. The method of claim 1, wherein the trench has an upper part and a lower part, the diameter of the upper part is greater than the diameter of the lower part, the first dielectric layer, the shield layer, and the spacer layer are disposed in the lower part, the second dielectric layer and the gate are disposed in the upper part.

6. A semiconductor device, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a first dielectric layer disposed in the epitaxial layer;

a shield layer disposed in the first dielectric layer;

a second dielectric layer disposed in the epitaxial layer;

a gate disposed in the second dielectric layer;

a spacer layer disposed between the first dielectric layer and the second dielectric layer, wherein the spacer layer directly contacts the epitaxial layer and separates the first dielectric layer and the second dielectric layer, the spacer layer is made of PolySilicon, the dopant ion concentration of the spacer layer is greater than the dopant ion concentration of the epitaxial layer, and a part of the first dielectric layer is disposed between the spacer layer and the shield layer, such that the spacer layer is electrically isolated from the shield layer; and

a source disposed in the epitaxial layer surrounding the second dielectric layer.

7. The semiconductor device of claim 6, further comprising:

a barrier layer disposed between the shield layer and the spacer layer.

8. The semiconductor device of claim 7, wherein the barrier layer is made of silicon nitride.

9. The semiconductor device of claim 6, further comprising:

a barrier layer disposed between the shield layer and the epitaxial layer.

10. The semiconductor device of claim 6, wherein the width of the first dielectric layer and the spacer layer is less than the width of the second dielectric layer.

11. A semiconductor device, comprising:

a substrate;

a first dielectric layer disposed in the substrate;

a shield layer disposed in the first dielectric layer;

a spacer layer disposed on the first dielectric layer and the substrate, wherein the spacer layer is made of PolySilicon, and a part of the first dielectric layer is disposed between the spacer layer and the shield layer, such that the spacer layer is electrically isolated from the shield layer;

an epitaxial layer disposed on the spacer layer, wherein the spacer layer directly contacts the epitaxial layer, and the dopant ion concentration of the spacer layer is greater than the dopant ion concentration of the epitaxial layer;

a second dielectric layer disposed in the epitaxial layer, wherein the spacer layer separates the first dielectric layer and the second dielectric layer;

a gate disposed in the second dielectric layer; and

a source disposed in the epitaxial layer surrounding to the second dielectric layer.