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Fabrication of vertical field effect transistor structure with strained channels

  • US 9,755,073 B1
  • Filed: 05/11/2016
  • Issued: 09/05/2017
  • Est. Priority Date: 05/11/2016
  • Status: Active Grant
First Claim
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1. A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, comprising:

  • forming one or more vertical fins on a substrate;

    forming one or more doped regions in the substrate above which each of the one or more vertical fins is formed, wherein each of the one or more doped regions forms a bottom source/drain for one vertical field effect transistor;

    forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins;

    forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks;

    forming an anchor wall adjacent to and in contact with one or more fin segment endwalls; and

    removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

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