Fabrication of vertical field effect transistor structure with strained channels

• US 9,755,073 B1
• Filed: 05/11/2016
• Issued: 09/05/2017
• Est. Priority Date: 05/11/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Li, Juntao
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/152,080
• Time in Patent Office: 482 Days
• Field of Search: 257288, 257329, 257392, 257E2119, 438268, 438514, 438585
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

Claims

1. A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, comprising:

forming one or more vertical fins on a substrate;

forming one or more doped regions in the substrate above which each of the one or more vertical fins is formed, wherein each of the one or more doped regions forms a bottom source/drain for one vertical field effect transistor;

forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins;

forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks;

forming an anchor wall adjacent to and in contact with one or more fin segment endwalls; and

removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

2. The method of claim 1, further comprising forming a top source/drain on a top surface of the one or more vertical fins, where the vertical fin(s) form a channel of the vertical finFET.

3. The method of claim 1, wherein the one or more vertical fins are formed by forming a hardmask layer on the substrate and a photo mask layer on the hardmask layer, patterning the photomask layer and etching the hardmask layer to form one or more hardmask fin templates defining the width, length, and pitch of the one or more vertical fins.

4. The method of claim 1, wherein the sacrificial stressor layer is a flowable oxide.

5. The method of claim 1, wherein the anchor wall is a silicon nitride.

6. The method of claim 1, further comprising forming a fin-cut mask on a top surface of the one or more vertical fins and sacrificial stressor layer, and forming one or more fin-cut mask trench(es) in the fin-cut mask to define the position and width of the fin trench.

7. The method of claim 6, further comprising forming a gate structure on the one or more vertical fins.

8. A method of forming a vertical finFET with a strained channel, comprising:

forming a plurality of vertical fins on a substrate;

forming a sacrificial stressor layer adjacent to the vertical fins, wherein the sacrificial stressor layer is in contact with the sidewalls of the adjacent vertical fins, and imparts a compressive strain to the adjacent vertical fins, wherein the compressive strain induced in the adjacent vertical fins is in the range of about 0.4 GPa to about 2 GPa;

forming a plurality of fin trenches through the plurality of vertical fins and the sacrificial stressor layer, where the fin trench separates the vertical fins into columns of fin segments and a plurality of sacrificial stressor layer blocks adjacent to two fin segments;

forming an anchor wall in each fin trench adjacent to and in contact with one or more fin segment endwalls; and

removing the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

9. The method of claim 8, further comprising forming a top source/drain on a top surface of the one or more vertical fins.

10. The method of claim 8, further comprising forming one or more doped regions in the substrate above which each of the one or more vertical fins is formed, wherein the doped region forms a bottom source/drain for a vertical field effect transistor.

11. The method of claim 8, wherein the sacrificial stressor layer is a flowable oxide.

12. The method of claim 8, wherein the sacrificial stressor layer is formed by CVD.

13. A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, comprising:

forming one or more vertical fins on a substrate;

forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a vertical compressive or tensile strain in the adjacent vertical fins;

forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks;

forming an anchor wall adjacent to and in contact with one or more fin segment endwalls; and

removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

14. The method of claim 13, wherein the compressive strain induced in the adjacent vertical fins is in the range of about 0.4 GPa to about 2 GPa.

15. The method of claim 13, wherein the sacrificial stressor layer is deposited over the one or more vertical fins by atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD).

16. The method of claim 15, further comprising heat treating the sacrificial stressor layer to reduce the volume of the sacrificial stressor layer.

17. The method of claim 13, further comprising, forming one or more doped regions in the substrate above which each of the one or more vertical fins is formed, wherein each of the one or more doped regions forms a bottom source/drain for one vertical field effect transistor.

18. The method of claim 17, further comprising forming a top source/drain on a top surface of the one or more vertical fins, where the vertical fin(s) form a channel of the vertical finFET, where the current flows in a vertical direction.