Injection-locked oscillator and method for controlling jitter and/or phase noise

• US 9,755,574 B2
• Filed: 07/28/2016
• Issued: 09/05/2017
• Est. Priority Date: 08/06/2015
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Chatwin, Jeremy
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US15/222,421
• Publication Number:
  US 20170040941A1
• Time in Patent Office: 404 Days
• Field of Search: 331 57, 331 46, 331 47, 327118
• CPC Class Codes: H03B 1/04 Reducing undesired oscillations, e.g. harmonics
• CPC Class Codes: H03B 2200/009 Reduction of phase noise
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

Claims

1. An injection-locked oscillator, comprising:

one or more circuits configured to;

receive a pair of complementary phase output signals from a gain stage of said injection-locked oscillator; and

a pair of shorting switches, arranged in parallel, and configured to;

receive a pair of switching signals; and

short, by said received pair of switching signals, said received pair of complementary phase output signals, wherein said short is configured to reduce a phase difference between an input signal and an output signal of said injection-locked oscillator.

2. The injection-locked oscillator according to claim 1, wherein said gain stage of said injection-locked oscillator comprise at least one of an inverter or a current mode logic (CML)-based circuitry.

3. The injection-locked oscillator according to claim 2, wherein said inverter is one of a complementary metal-oxide semiconductor (CMOS) based inverter or a current starved inverter.

4. The injection-locked oscillator according to claim 1, wherein said pair of shorting switches comprises a N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor configured to short said received pair of complementary phase output signals.

5. The injection-locked oscillator according to claim 1, wherein said pair of shorting switches comprises a N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor.

6. The injection-locked oscillator according to claim 1, wherein said pair of switching signals correspond to a pair of shorting pulses applied periodically to said pair of shorting switches for said shorting, wherein a duration of said shorting is one of fixed or configurable.

7. The injection-locked oscillator according to claim 1, wherein a number of said pair of shorting switches, which are enabled to receive a pair of shorting pulses, is determined based on a target injection strength to be achieved by said injection-locked oscillator.

8. The injection-locked oscillator according to claim 1, further comprises a plurality of gain stages arranged such that the pair of complementary phase output signals from a first gain stage of the plurality of gain stages is coupled to a pair of input signals of a second gain stage, wherein the second gain stage is subsequent to the first gain stage.

9. The injection-locked oscillator according to claim 1, wherein a rising transition of a first pair of complementary phase output signals of a first gain stage leads a second pair of complementary phase output signals of a second gain stage, wherein the second gain stage is subsequent to the first gain stage.

10. The injection-locked oscillator according to claim 1, wherein a rising edge of said pair of complementary phase output signals is injection locked for a time period to an incoming signal phase by said shorting.

11. The injection-locked oscillator according to claim 1, wherein a falling edge of said pair of complementary phase output signals is injection locked for a time period to an incoming signal phase by said shorting.

12. The injection-locked oscillator according to claim 1, further comprises a resonator configured to adjust an output signal phase of said injection-locked oscillator for said reduction in said phase difference.

13. A method for reducing jitter, said method comprising:

receiving, by one or more circuits of an injection-locked oscillator, a pair of complementary phase output signals from a gain stage of said injection-locked oscillator;

receiving, by a pair of shorting switches arranged in parallel, a pair of switching signals; and

shorting, by said pair of shorting switches, said received pair of complementary phase output signals to reduce a phase difference between an input signal and an output signal of said injection-locked oscillator.

14. The method according to claim 13, wherein said gain stage of said injection-locked oscillator comprise at least one of an inverter or a current mode logic (CML)-based circuitry.

15. The method according to claim 13, wherein said pair of switching signals correspond to a pair of shorting pulses applied periodically to said pair of shorting switches of said injection-locked oscillator for said shorting, wherein a duration of said shorting is one of fixed or configurable.

16. The method according to claim 13, wherein a rising transition of a first pair of complementary phase output signals of a first gain stage leads a second pair of complementary phase output signals of a second gain stage, wherein the second gain stage is subsequent to the first gain stage.

17. The method according to claim 13, wherein a rising edge of said pair of complementary phase output signals is injection locked for a time period to an incoming signal phase by said shorting.

18. The method according to claim 13, wherein a falling edge of said pair of complementary phase output signals is injection locked for a time period to an incoming signal phase by said shorting.

19. The method according to claim 13, further comprising adjusting an output signal phase of said injection-locked oscillator for said reduction in said phase difference based on a resonator in said injection-locked oscillator.