Rail-to-rail comparator with shared active load

• US 9,755,619 B2
• Filed: 09/04/2016
• Issued: 09/05/2017
• Est. Priority Date: 10/21/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Zhi, Hao, Jin, Jie, Wang, Yang, Wu, Jianzhou
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US15/256,571
• Publication Number:
  US 20170117880A1
• Time in Patent Office: 366 Days
• Field of Search: 327 63, 327 64, 327 65, 327 66
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Claims

1. A comparator, comprising:

a n-type input stage connected to receive a differential input signal comprising a negative input component and a positive input component, wherein the n-type input stage comprises a differential pair of input n-channel transistors having their sources connected to a current sink, and a pair of active load p-channel transistors having their sources connected together, and their gates connected together and to a drain of a first one of the input n-channel transistors;

a p-type input stage connected to receive the differential input signal, wherein the p-type input stage comprises a differential pair of input p-channel transistors having their sources connected to a current source, and a pair of active load n-channel transistors having their sources connected together, and their gates connected together and to a drain of a first one of the input p-channel transistors;

a shared-load stage connected to both the n-type input stage and the p-type input stage and comprising load devices that are shared by both the n-type input stage and the p-type input stage; and

an output stage connected to the shared-load stage, wherein the output stage comprises a first output transistor having a source connected to the sources of the active load p-channel transistors and a gate connected to the shared-load stage, and a second output transistor having a source connected to the sources of the active load n-channel transistors and a gate connected to the shared-load stage, and configured to present a comparator output signal indicative of relative voltage levels of the differential input signal at a node between the drains of the first and second output transistors,

wherein the p-type input stage is configured to be inactive, if a common-mode voltage of the differential input signal is substantially close to a power rail of the comparator, and the n-type input stage is configured to be inactive, if the common-mode voltage of the differential input signal is substantially close to a ground rail of the comparator.

2. The comparator of claim 1, wherein

the first n-type transistor of the input n-channel transistors has a gate node connected to receive the positive input component, and a second n-type transistor of the input n-channel transistors has a gate node connected to receive the negative input component;

and

the p-channel active-load transistors are connected to a drain node of one of the first and second n-type transistors, wherein at least one of the active-load transistors is connected to the shared-load stage.

3. The comparator of claim 2, wherein the active-load p-channel transistors comprise:

a first p-type active-load transistor having a gate node and a drain node connected to the drain node of the one of the first and second n-type transistors; and

a second p-type active-load transistor having a gate node connected to the drain node of the one of the first and second n-type transistors and a drain node connected to the shared-load stage.

4. The comparator of claim 2, wherein

the first p-type transistor of the input p-channel transistors has a gate node connected to receive the positive input component, and a second p-type transistor of the input p-channel transistors has a gate node connected to receive the negative input component;

and

the n-channel active-load transistors are connected to a drain node of one of the first and second p-type transistors, wherein at least one of the active-load transistors is connected to the shared-load stage.

5. The comparator of claim 4, wherein the active load n-channel transistors comprise:

a first n-type active-load transistor having a gate node and a drain node connected to the drain node of the one of the first and second n-type transistors; and

a second n-type active-load transistor having a gate node connected to the drain node of the one of the first and second n-type transistors and a drain node connected to the shared-load stage.

6. The comparator of claim 1, wherein the shared-load stage comprises:

at least one p-type shared-load transistor and one n-type shared-load transistor, each shared-load transistor connected to the p-type input stage, the n-type input stage, and the output stage.

7. The comparator of claim 6, wherein:

a p-type shared-load transistor has a gate and a drain connected to the p-type input stage, the n-type input stage, and the output stage; and

an n-type shared-load transistor has a gate and a drain connected to the p-type input stage, the n-type input stage, and the output stage.

8. The comparator of claim 1, wherein:

the p-type input stage is configured to be inactive, if the common-mode voltage of the differential input signal is greater than (Vdd−

V_dsatP−

V_thP), where Vdd is a power supply voltage applied to the power rail for the comparator, V_dsatP is the minimum voltage drop across the current source, when the current source is operating properly, and V_thP is the threshold voltage of the p-type transistors, and

the n-type input stage is configured to be inactive, if the common-mode voltage of the differential input signal is less than (V_dsatN+V_thN), where V_dsatN is the minimum voltage drop across the current sink, when the current sink is operating properly, and V_thN is the threshold voltage of the n-type transistors.

9. The comparator of claim 1, wherein when one of the p-type and n-type stages is inactive, the remaining stage operates with no more than 9 active transistors.

10. The comparator of claim 1, wherein the transistors are field-effect transistors.

11. The comparator of claim 1, wherein the comparator circuit comprises no more than 14 transistors.

12. A comparator, comprising:

an NMOS-input stage comprising a differential pair of source-coupled n-type transistors and one or more NMOS-input stage active-load transistors, wherein a first of the source-coupled n-type transistors is electrically connected via its gate node to a positive differential input node and a second of the n-type transistors is electrically connected at its gate node to a negative input node, wherein the NMOS-input stage active-load transistors have their gates connected together and to a drain of one of the differential pair of source-coupled n-type transistors, and the sources of the differential pair of source-coupled n-type transistors are connected to a current sink;

a PMOS-input stage comprising a differential pair of source-coupled p-type transistors and one or more PMOS-input stage active-load transistors, wherein a first of the source-coupled p-type transistors is electrically connected via its gate node to the positive differential input node and a second of the source-coupled p-type transistors is electrically connected via its gate node to the negative input node, wherein the PMOS-input stage active-load transistors have their gates connected together and to a drain of one of the differential pair of source-coupled p-type transistors, and the sources of the differential pair of source-coupled p-type transistors are connected to a current source;

a shared-load stage comprised of first and second active-load transistors that are electrically connected between the PMOS-input stage and the NMOS-input stage, wherein the first active-load transistor of the shared-load stage has a source connected to the sources of the NMOS-input stage active-load transistors, a drain connected to the drain of one of the differential pair of source-coupled n-type transistors of the NMOS input stage, and a gate connected to its drain, and the second active-load transistor of the shared-load stage is connected between the active-load transistors of the NMOS- and PMOS-input stages; and

an output stage that includes no more than two transistors, wherein gates of the output stage transistors are electrically connected to gates of the first and second active-load transistors of the shared-load stage,

wherein in operation, when the NMOS-input stage is active, the current is drawn through at least one of the active-load transistors within the shared-load stage, and when the PMOS-input stage is active, the current is drawn through the same at least one of the active-load transistors within the shared-load stage.

13. The comparator of claim 12, wherein when the common-mode voltage is very high or very low, only one of the PMOS- and NMOS-input stages is operational.

14. The comparator of claim 13, wherein within the operational stage has no more than nine (9) transistors are active at a time.

15. The comparator of claim 12, wherein the transistors are bipolar.