Interface circuit

• US 9,755,644 B2
• Filed: 09/29/2016
• Issued: 09/05/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Yamada, Takashi
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US15/279,574
• Publication Number:
  US 20170093402A1
• Time in Patent Office: 341 Days
• Field of Search: None
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

An interface circuit includes at least one semiconductor logic gate and a latch circuit. The semiconductor logic gate configured to receive an input signal having a signal level changeable and outputs a logic gate signal which has a signal level becoming a low level when a signal level of the input signal is not less than a logic threshold value, alternatively has a signal level becoming a high level when a signal level of the input signal is less than the logic threshold value. The latch circuit fetches the logic gate signal as a first latch signal, while fetching a signal which is converted from the input signal and has a signal level varying between a second voltage and the ground potential, alternatively, the input signal as a second latch signal, to output the first interface output signal and the second interface output signal.

Claims

1. An interface circuit configured to receive a first voltage and a second voltage and generate an interface output signal based on an input signal, the interface circuit comprising:

a first semiconductor logic gate which receives said first voltage and outputs a first output signal of low level when a signal level of said input signal is not less than a logic threshold value, alternatively outputs said first output signal of high level in response to said first voltage when a signal level of said input signal is less than said logic threshold value;

a second semiconductor logic gate which receives said second voltage and outputs a second output signal of low level when a signal level of said input signal is not less than a logic threshold value, alternatively outputs said second output signal of high level in response to said second voltage when a signal level of said input signal is less than said logic threshold value;

a third semiconductor logic gate which receives said second voltage and outputs a third output signal of low level when a signal level of said first output signal is not less than a logic threshold value, alternatively outputs said third output signal of high level in response to said second voltage when a signal level of said first output signal is less than said logic threshold value; and

a latch circuit which receives said second output signal and said third output signal and generates a 4th output signal and a 5th output signal to output said 4th output signal or said 5th output signal as said interface output signal, wherein

said latch circuit generates said 4th output signal having an inversed signal level from said second output signal and said 5th output signal having an inversed signal level from said third output signal in a first state in which one of said second output signal and said third output signal is a low level,

when, after said first state, both said second output signal and said third output signal transit to a second state of high level, said latch circuit generates said 4th output signal and said 5th output signal holding the respective signal levels of said first state just before transition to said second state.

2. The interface circuit according to claim 1, wherein

said input signal has a potential in response to said first voltage in the high level and a ground potential in the low level.

3. The interface circuit according to claim 1, wherein

said first semiconductor logic gate outputs said first output signal having a ground potential in the low level,

said second semiconductor logic gate outputs said second output signal having the ground potential in the low level, and

said third semiconductor logic gate outputs said third output signal having the ground potential in the low level.

4. The interface circuit according to claim 1, wherein

said first voltage is an external power supply voltage supplied from an outside, and

said second voltage is a voltage voltage-converted from said first voltage by a voltage convert circuit.

5. The interface circuit according to claim 1, wherein

said first semiconductor logic gate includes a first transistor of first conductive type and a second transistor of second conductive type opposite to said first conductivity type which are connected to each other at respective drain terminals, and

said second semiconductor logic gate includes a third transistor of said first conductivity type and a 4th transistor of said second conductivity type which are connected to each other at respective drain terminals, and

said third semiconductor logic gate a 5th transistor of said first conductivity type and a 6th transistor of said second conductivity type which are connected to each other at respective drain terminals, and

said first transistor has a source terminal to which said first voltage is applied, and

said second transistor has a source terminal being grounded, and

said third transistor has a source terminal to which said second voltage is applied, and

said 4th transistor has a source terminal being grounded, and

said 5th transistor has a source terminal to which said second voltage is applied, and

said 6th transistor has a source terminal being grounded.

6. The interface circuit according to claim 1, wherein

said latch circuit includes a first NAND circuit and a second NAND circuit.

7. The interface circuit according to claim 1, wherein

a logic threshold value of said first semiconductor logic gate, the logic threshold value of said second semiconductor logic gate and the logic threshold value of said third semiconductor logic gate are equal to one another.

8. An interface circuit configured to receive a first voltage and a second voltage and generate an interface output signal based on an input signal, the interface circuit comprising:

a first semiconductor logic gate which receives said first voltage and outputs a first output signal in response to said input signal;

a second semiconductor logic gate which receives said second voltage and outputs a second output signal in response to said input signal;

a third semiconductor logic gate which receives said second voltage and outputs a third output signal in response to said first output signal; and

a latch circuit which receives said second output signal and said third output signal being input and generates said interface output signal, wherein

said latch circuit outputs an output value, as said interface output signal, reflecting said second output signal and said third output signal when said second output signal and said third output signal being input have logic values different from each other,

when both logic values of said second output signal and said third output signal being input are the same, said latch circuit maintains said output value just before both the logic values become the same and outputs said output value as said interface output signal.

9. An interface circuit configured to receive a first voltage and a second voltage and generate an interface output signal based on an input signal, the interface circuit comprising:

a semiconductor logic gate configured to receive the input signal having a signal level changeable between the first voltage and a ground potential and to output a logic gate signal which has a signal level becoming a low level when a signal level of said input signal is not less than a logic threshold value, and, alternatively has a signal level becoming a high level when a signal level of said input signal is less than said logic threshold value; and

a latch circuit which fetches said logic gate signal as a first latch signal, while fetching a signal which is converted from said input signal and has a signal level varying between the second voltage and the ground potential, and which fetches, alternatively, said input signal as a second latch signal, to output the first interface output signal and the second interface output signal,

wherein said latch circuit outputs a signal having an inversed signal level from the signal level of said first latch signal as said first interface output signal and outputs a signal having an inversed signal level from the signal level of said second latch signal as said second interface output signal in a first state in which only one of said first latch signal and second latch signal is a low level, and

when both said first latch signal and said second latch signal transit from said first state to a second state in which both said first latch signal and said second latch signal are in a high level or in a low level, said latch circuit outputs at least one of said first interface output signal and said second interface output signal holding the respective signal levels of said first state just before transition from said second state to said second state.

10. The interface circuit according to claim 9, wherein

said latch circuit fetches said input signal as said second latch signal,

said latch circuit generates, in said first state, a signal having an inversed signal level from said logic gate signal as said first interface output signal and a signal having an inversed signal level from said input signal as said second interface output signal.

11. The interface circuit according to claim 10, wherein

said latch circuit includes a first NOR circuit and a second NOR circuit.

12. The interface circuit according to claim 10, wherein said first NOR circuit includes

a first transistor of first conductive type having a source terminal to which said second voltage is applied,

a second transistor of second conductive type opposite to said first conductivity type having a source terminal being grounded and a gate terminal receiving said input signal,

a third transistor of said first conductivity type having a source terminal connected to a drain terminal of said first transistor, and

a 4th transistor of said second conductivity type having a source terminal being grounded, a drain terminal connected to a drain terminal of said third transistor, and a gate terminal receiving said second interface output signal, wherein said second NOR circuit includes

a 5th transistor of said first conductivity type having a source terminal to which said second voltage is applied,

a 6th transistor of said second conductivity type having a source terminal being grounded and a gate terminal receiving said logic gate signal,

a 7th transistor of said first conductivity type having a source terminal to which the drain terminal of said 5th transistor is connected, and

an 8th transistor of said second conductivity type having a source terminal being grounded and a drain terminal to which the drain terminal of said 7th transistor is connected and a gate terminal receiving said second interface output signal.

13. The interface circuit according to claim 12, wherein

said first transistor, said second transistor, said 5th transistor and said 6th transistor are high breakdown voltage transistors;

said third transistor, said 4th transistor, said 7th transistor and said 8th transistor are low breakdown voltage transistors;

said first transistor receives said input signal at the gate terminal;

said third transistor receives said interface output signal at the gate terminal;

said 5th transistor receives said logic gate signal at the gate terminal; and

said 7th transistor receives said second interface output signal at the gate terminal.

14. The interface circuit according to claim 12, wherein

said first transistor, said 4th transistor, said 5th transistor and said 8th transistor are low breakdown voltage transistors;

said second transistor, said third transistor, said 6th transistor and said 7th transistor are high breakdown voltage transistors;

said first transistor receives said interface output signal at the gate terminal;

said third transistor receives said input signal at the gate terminal;

said 5th transistor receives said second interface output signal at the gate terminal; and

said 7th transistor receives said logic gate signal.

15. An interface circuit configured to receive a first voltage and a second voltage and generate an interface output signal based on an input signal, the interface circuit comprising:

a latch circuit to which the input signal and said first voltage are supplied, the input signal having a signal level changeable between the first voltage and a ground potential, to output the output signal,

wherein said latch circuit outputs said output signal as a signal having a signal level varying with an opposite phase to said input signal in a first state in which the voltage level of said first voltage is higher than the logic threshold value, and

when the voltage level of said first voltage transit from said first state to a second state in which the voltage level of said first voltage is less than said logic threshold value, said latch circuit outputs holding the signal level in said first state just before transition to said second state.

16. The interface circuit according to claim 15, wherein said latch circuit includes a first NOR circuit and a second NOR circuit.