Selectively disabled output

• US 9,755,650 B1
• Filed: 06/16/2016
• Issued: 09/05/2017
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Reese, Laura
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Kim, Seokjin
• Application Number:
  US15/184,921
• Time in Patent Office: 446 Days
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17768 for security

Abstract

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Claims

1. An integrated circuit device, comprising:

a storage circuit that stores first data;

a device package comprising a first power supply pin and a second power supply pin;

a first power supply pad electrically coupled to the first power supply pin;

a second power supply pad electrically coupled to the second power supply pin, wherein the integrated circuit device operates using electrical power received when a first voltage is applied to the first power supply pin and a second voltage is applied to the second power supply pin;

an input pad selectively connected affixedly to one of the first power supply pin and the second power supply pin; and

a readout circuit communicatively coupled to the storage circuit and electrically coupled to the input pad via a first circuit line, wherein the readout circuit;

enables readout of the first data from the integrated circuit device when the input pad is electrically connected affixedly to the second power supply pin and the second voltage is applied to the input pad via the second power supply pin; and

disables the readout of the first data from the integrated circuit device when the input pad is electrically connected affixedly to the first power supply pin and the first voltage is applied to the input pad via the first power supply pin, wherein the integrated circuit device does not operate properly when the second voltage is supplied to the first power supply pin to facilitate preventing readout of the first data from the integrated circuit device while the input pad is electrically connected affixedly to the first power supply pin.

2. The integrated circuit device of claim 1, wherein:

the first power supply pad comprises a VCC pad;

the first power supply pin comprises a VCC pin;

the second power supply pad comprises a GND pad; and

the second power supply pin comprises a GND pin.

3. The integrated circuit device of claim 1, wherein the integrated circuit device operates properly when the first voltage is a positive voltage and the second voltage is a ground voltage.

4. The integrated circuit device of claim 1, wherein:

the input pad is electrically connected affixedly to the second power supply pin while debugging design of the integrated circuit device;

the input pad is electrically connected affixedly to the first power supply pin after debugging the design of the integrated circuit device; and

the device package restricts user access to the input pad after the input pad is electrically connected affixedly to the first power supply pin.

5. The integrated circuit device of claim 1, wherein the integrated circuit device does not operate properly when a third voltage different from the first voltage is applied to the first power supply pin.

6. The integrated circuit device of claim 1, wherein the readout circuit disables the readout of the first data by outputting second data different from the first data.

7. The integrated circuit device of claim 1, comprising:

an output port communicatively coupled to the readout circuit via a second circuit line; and

a disabling element that breaks the first circuit line, the second circuit line, or both when the input pad is electrically connected affixedly to the second power supply pin.

8. A method for manufacturing a programmable logic device used to store first data, comprising:

electrically connecting a first power supply pad to a first power supply pin formed on a device package to facilitate receiving electrical power used to operate the programmable logic device when a first voltage is applied to the first power supply pin;

electrically connecting a second power supply pad to a second power supply pin formed on the device package to facilitate receiving the electrical power when a second voltage is applied to the second power supply pin;

electrically connecting affixedly an input pad to the second power supply pin to facilitate debugging design of the programmable logic device by enabling the programmable logic device to output the first data when the second voltage is applied to the input pad via the second power supply pin; and

electrically connecting affixedly the input pad to the first power supply pin to disable the output of the first data from the programmable logic device after debugging the design, wherein the programmable logic device;

disables the output of the first data from the integrated circuit device when the input pad is electrically connected affixedly to the first power supply pin and the first voltage is applied to the input pad via the first power supply pin; and

does not operate properly when the second voltage is supplied to the first power supply pin to facilitate preventing the output of the first data from the programmable logic device while the input pad is electrically connected affixedly to the first power supply pin.

9. The method of claim 8, wherein:

electrically connecting the first power supply pad to the first power supply pin facilitates receiving the electrical power by causing the first power supply pad to be at a positive voltage when the first voltage is applied to the first power supply pin; and

electrically connecting the second power supply pad to the second power supply pin facilitates receiving the electrical power by causing the second power supply pad to be at a ground voltage when the second voltage is applied to the second power supply pin.

10. The method of claim 8, comprising forming the device package to restrict accessibility of the input pad after the input pad is electrically connected affixedly to the first power supply pin.

11. The method of claim 8, comprising:

communicatively coupling a storage circuit that stores the first data to an output port of the programmable logic device via a circuit line; and

breaking, using a disabling element, the circuit line when the input pad is electrically connected affixedly to the first power supply pin and the first voltage is applied to the first power supply pin.

12. The method of claim 8, comprising causing the programmable logic device to output second data different from the first data when the input pad is electrically connected affixedly to the first power supply pin.

13. The method of claim 8, wherein:

the first data comprises configuration data used to program operation of the programmable logic device, internal data indicative of the configuration data, or both; and

electrically connecting affixedly the input pad to the second power supply pin facilitates debugging the design of the programmable logic device by facilitating;

detecting occurrence of an error during operation of the programmable logic device based at least in part on the output of the first data; and

correcting the error by adjusting the design of the programmable logic device.

14. The method of claim 8, comprising communicatively coupling configuration data memory of the programmable logic device with external memory to enable the programmable logic device to:

receive configuration data from the external memory, wherein the first data comprises the configuration data; and

store the configuration data in the configuration data memory.

15. An electronic system, comprising:

a programmable logic device that operates using electrical power to perform logical functions in the electronic system, wherein the programmable logic device comprises;

configuration data memory that stores configuration data;

a plurality of logic blocks programmed based at least in part on the configuration data;

a first power supply pin and a second power supply pin that facilitate receiving the electrical power used to operate the programmable logic device when a first voltage is applied to the first power supply pin and a second voltage is applied to the second power supply pin; and

an input pad, wherein the programmable logic device;

enables output of the configuration data from the programmable logic device when the input pad is electrically connected affixedly to the second power supply pin and the second voltage is applied to the input pad via the second power supply pin; and

disables the output of the configuration data from the programmable logic device when the input pad is electrically connected affixedly to the first power supply pin and the first voltage is applied to the input pad via the first power supply pin, wherein the programmable logic device does not function properly when the second voltage is supplied to the first power supply pin to facilitate preventing the output of the configuration data from the programmable logic device while the input pad is electrically connected affixedly to the first power supply pin.

16. The electronic system of claim 15, wherein the first power supply pin is at a positive voltage and the second power supply pin is at a ground voltage when the electrical power is supplied to the programmable logic device.

17. The electronic system of claim 15, wherein the programmable logic device comprises a device package that blocks user access to the input pad.

18. The electronic system of claim 15, comprising a processing unit that controls operation of the electronic system, wherein:

the processing unit comprises the programmable logic device without a central processing unit; and

the processing unit comprises a floating point coprocessor.

19. The electronic system of claim 15, wherein:

the programmable logic device comprises an embedded microprocessor;

the programmable logic device comprises a distributed memory structure;

or both.

20. The electronic system of claim 15, wherein the electronic system comprises a digital computer system, a digital signal processing system, a specialized digital switching network, a telecommunications system, an automotive system, or a control system.