Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes

• US 9,755,818 B2
• Filed: 09/19/2014
• Issued: 09/05/2017
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro
• Primary Examiner(s): NGUYEN, LEON VIET Q
• Application Number:
  US14/491,884
• Publication Number:
  US 20150098537A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Claims

1. A method of data communications, comprising:

monitoring a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;

detecting a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, and wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;

generating an edge on a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period; and

capturing data received from the plurality of data lanes using the receiver clock signal.

2. The method of claim 1, further comprising:

deserializing data received from one or more data lanes using the receiver clock signal.

3. The method of claim 1, wherein the timing signal carried on the timing lane is a double data rate clock signal aligned with data received from the data lane.

4. The method of claim 1, wherein each data lane in the plurality of data lanes is carried on a pair of differentially driven wires.

5. The method of claim 1, further comprising:

comparing a first symbol representative of a signaling state of the plurality of data lanes during the first data period with a second symbol representative of the signaling state of the plurality of data lanes during the second data period.

6. The method of claim 1, wherein the receiver clock signal is unaffected by one or more additional transitions on the data communications link occurring in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

7. The method of claim 6, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.

8. An apparatus comprising:

means for detecting a first-occurring transition on a data communications link, whether the first-occurring transition occurs in a data lane of a data communications link or in a timing lane of the data communications link, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period, wherein the means for detecting is configured to monitor a plurality of data signals carried on a plurality of data lanes and a timing signal carried on the timing lane, and wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;

means for generating an edge of a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period; and

means for decoding data received from the plurality of data lanes using the receiver clock signal.

9. The apparatus of claim 8, wherein the means for decoding the data received from the data lane is configured to deserialize data received from one or more data lanes.

10. The apparatus of claim 8, wherein the timing signal carried on the timing lane is a double data rate clock signal.

11. The apparatus of claim 10, wherein transitions of the double data rate clock signal are aligned with transitions of the data received from the data lane.

12. The apparatus of claim 8, wherein the means for detecting the first-occurring transition is configured to:

compare a first symbol representative of a signaling state of the plurality of data lanes during the first data period with a second symbol representative of the signaling state of the plurality of data lanes during the second data period.

13. The apparatus of claim 8, wherein the receiver clock signal is unaffected by one or more additional transitions on the data communications link occurring in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

14. The apparatus of claim 13, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.

15. An apparatus, comprising:

a processing circuit configured to;

monitor a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;

detect a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;

generate an edge on a receiver clock signal based on the first-occurring transition; and

capture data received from the plurality of data lanes using the receiver clock signal, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period.

16. The apparatus of claim 15, wherein the processing circuit configured to deserialize data received from one or more data lanes using the receiver clock signal.

17. The apparatus of claim 15, wherein the timing signal carried on the timing lane is a double data rate clock signal.

18. The apparatus of claim 17, wherein transitions of the double data rate clock signal are aligned with transitions of the data received from the data lane.

19. The apparatus of claim 15, wherein the receiver clock signal is unaffected by one or more additional transitions occurring on the data communications link in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

20. The apparatus of claim 19, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.

21. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

monitor a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;

detect a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, and wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;

generate an edge on a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period; and

capture data received from the plurality of data lanes using the receiver clock signal.

22. The non-transitory processor-readable storage medium of claim 21, wherein the receiver clock signal is used to deserialize data received from one or more data lanes.

23. The non-transitory processor-readable storage medium of claim 21, wherein the timing signal carried on the timing lane is a double data rate clock signal.

24. The non-transitory processor-readable storage medium of claim 23, wherein transitions of the double data rate clock are aligned with transitions of the data received from the data lane.

25. The non-transitory processor-readable storage medium of claim 21, wherein the receiver clock signal is unaffected by one or more additional transitions occurring in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

26. The non-transitory processor-readable storage medium of claim 25, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.