Transmission of delay tolerant data
First Claim
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1. An apparatus comprising:
- a processor configured to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data, and to control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is postponed until availability of the delay critical data and to coincide with transmission of the delay critical data; and
a buffer configured to store the delay tolerant data,wherein the processor is further configured to start a timer when detecting the delay tolerant data, and if the timer expires before the transmission of the delay tolerant data is possible simultaneously with the transmission of the delay critical data, the processor is further configured to control the transmitter in such a manner that the transmission of the delay tolerant data is performed irrespective of the transmission of the delay critical data.
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Abstract
Transmission of delay tolerant data. An apparatus includes a processor configured to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data, and to control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is timed to coincide with transmission of the delay critical data.
13 Citations
17 Claims
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1. An apparatus comprising:
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a processor configured to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data, and to control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is postponed until availability of the delay critical data and to coincide with transmission of the delay critical data; and a buffer configured to store the delay tolerant data, wherein the processor is further configured to start a timer when detecting the delay tolerant data, and if the timer expires before the transmission of the delay tolerant data is possible simultaneously with the transmission of the delay critical data, the processor is further configured to control the transmitter in such a manner that the transmission of the delay tolerant data is performed irrespective of the transmission of the delay critical data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus comprising:
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a processor configured to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data, and to control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is postponed until availability of the delay critical data and to coincide with transmission of the delay critical data; and a buffer configured to store the delay tolerant data, wherein in case of the buffer becomes full, the processor is further configured to transmit the delay tolerant data or a portion of the delay tolerant data, even without its transmission coinciding with the transmission of the delay critical data. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus comprising:
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a processor; and a memory configured to store a computer program, wherein the memory and computer program are configured to, with the processor, cause the apparatus at least to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data; control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is postponed until availability of the delay critical data and to coincide with transmission of the delay critical data; start a timer when detecting the delay tolerant data; and if the timer expires before the transmission of the delay tolerant data is possible simultaneously with the transmission of the delay critical data, control the transmitter in such a manner that the transmission of the delay tolerant data is performed irrespective of the transmission of the delay critical data.
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Specification