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Line buffer unit for image processor

  • US 9,756,268 B2
  • Filed: 04/23/2015
  • Issued: 09/05/2017
  • Est. Priority Date: 04/23/2015
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a line buffer unit circuit comprised of a plurality of line buffer interface unit circuits, each line buffer interface unit circuit to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory, the line buffer unit circuit having programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory, wherein said line buffer unit circuit includes control logic circuitry to;

    assign at least one of the line buffer interface unit circuits to a free pool, that includes free ones of the line buffer interface unit circuits, after said at least one of the line buffer interface unit circuits has serviced its last consumer; and

    ,assign said at least one of the line buffer interface unit circuits from the free pool to another line group.

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