Ground fault detector

• US 9,759,758 B2
• Filed: 04/17/2015
• Issued: 09/12/2017
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Leviton Manufacturing Company Incorporated
• Original Assignee: Leviton Manufacturing Company Incorporated
• Inventors: Ostrovsky, Michael, Aronov, Alek, Kamor, Michael, Mathew, Renjith
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): MCANDREW, CHRISTOPHER P
• Application Number:
  US14/690,247
• Publication Number:
  US 20150309105A1
• Time in Patent Office: 879 Days
• Field of Search: 324133
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: H02H 3/335 the main function being self testing of the device

Abstract

An apparatus includes an interruption circuit in a power delivery path, and a fault detection circuit configured to provide a fault signal to selectively cause the interruption circuit to interrupt power delivery, wherein the fault detection circuit includes a fault detection integrated circuit and a sensing coil configured to sense a differential current between a phase conductive path and a neutral conductive path in the power delivery path. A processor is configured to selectively control a fault simulation circuit to simulate a fault in the power delivery path, detect a response of the fault detection circuit to the simulated fault, and determine if the response of the fault detection circuit is an expected response. The processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

Claims

1. An apparatus, comprising:

an interruption circuit electrically connected in a power delivery path, the power delivery path including a phase conductive path and a neutral conductive path;

a silicon-controlled rectifier (SCR) coupled to the interruption circuit and configured to cause the interruption circuit to interrupt power delivery in at least one of the phase conductive path and the neutral conductive path;

a fault detection circuit coupled to the SCR and configured to provide a first trigger signal to the SCR, wherein the fault detection circuit includes a sensing coil configured to sense a differential current between the phase conductive path and the neutral conductive path, and further includes a comparator-type fault detection integrated circuit (IC) that compares the differential current to a threshold;

a processor coupled to the fault detection circuit and to the SCR, wherein the processor is configured to;

identify when the fault detection circuit provides the first trigger signal;

identify whether the SCR is able to cause the interruption circuit to interrupt power delivery upon receipt of the first trigger signal during a power half-cycle in which the first trigger signal is provided; and

in the case in which it is identified that the SCR is not able to cause the interruption circuit to interrupt power delivery during the power half-cycle in which the first trigger signal is provided, provide a second trigger signal to the SCR in a subsequent power half-cycle.

2. The apparatus of claim 1, further comprising:

a fault simulation circuit;

wherein the processor is further coupled to the fault simulation circuit, and the processor configured to;

selectively control the fault simulation circuit to simulate a fault in the power delivery path; and

provide an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

3. The apparatus of claim 1, wherein the processor is powered from line side conductors.

4. The apparatus of claim 1, the processor further configured to:

receive an indication that the fault detection circuit has provided the fault signal;

receive an indication that a reset button has been pushed;

initiate a self-test including a fault simulation; and

if the self-test passes, provide a release signal to an electronic switch component to unlatch and thereby allow the interruption circuit to remove an interruption of power delivery; and

if the self-test does not pass, prevent the interruption circuit from removing the interruption of power delivery.

5. The apparatus of claim 1, wherein power delivery is interrupted by the latching of the SCR in a conductive state in response to a received fault signal, and wherein the SCR is powered from a rectified power signal or an alternating current power line such that the SCR may only be latched during one power half-cycle;

the processor further configured to;

receive an indication that a manual reset button has been pushed;

initiate a self-test including self-testing in two power half-cycles of opposite polarity to ensure that the SCR will latch in response to a fault signal received during a self-test in one of the two power half-cycles.

6. The apparatus of claim 1, further comprising a rectifier, wherein the processor is configured to, prior to initiating a fault simulation, determine the rate of zero crossings of an amplitude of the output of the rectifier to identify a failure of a component in the rectifier, and if a failure of a component in the rectifier is detected, the processor does not initiate a fault simulation.

7. The apparatus of claim 1, further comprising:

a fault simulation circuit configured to selectively cause a current imbalance between the phase conductive path and the neutral conductive path;

wherein the processor is further coupled to the fault simulation circuit and is further configured to;

selectively control the fault simulation circuit to cause a first current imbalance to simulate a fault during a first power half-cycle; and

detect a response of the fault detection circuit to the simulated fault;

wherein the processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

8. The apparatus of claim 7, wherein the processor is configured to selectively control the fault simulation circuit to cause the first current imbalance starting at a predetermined time after the beginning of the first power half-cycle.

9. The apparatus of claim 7, wherein the first power half-cycle is randomly either a positive polarity or a negative polarity.

10. The apparatus of claim 7, wherein the processor is configured to control the fault simulation circuit to cause a second current imbalance during a second power half-cycle.

11. The apparatus of claim 10, wherein the first power half-cycle and the second power half-cycle have approximately opposite polarity.

12. The apparatus of claim 10, wherein the end of the first power half-cycle and the beginning of the second power half-cycle are separated in time by an even number of power half-cycles.

13. The apparatus of claim 10, wherein the processor is configured to control the fault simulation circuit to cause the first current imbalance during a portion of the first power half-cycle and to cause a second current imbalance during a portion of the second power half-cycle, each portion beginning several milliseconds after the start of the respective half-cycle.

14. The apparatus of claim 1, further comprising:

a fault simulation circuit;

wherein the processor is coupled to the fault simulation circuit and is further configured to selectively control the fault simulation circuit to simulate a fault in the power delivery path and detect a response of the fault detection circuit to the simulated fault; and

a power circuit including a solenoid coil, a rectifier, and a first resistor in parallel with the solenoid coil, wherein the processor and the fault detection circuit are powered from a line side of the power delivery path via the solenoid coil and rectifier, and the resistor is sized such that, if the solenoid coil is damaged, the resistor will not allow sufficient power for proper operation of both the processor and the fault detection circuit.

15. The apparatus of claim 14, further comprising:

a trigger circuit; and

a second resistor positioned between the fault detection circuit and the trigger circuit;

wherein the processor is further configured to monitor a voltage across the second resistor during a simulated fault, and determine from an amplitude of the voltage whether the value of a resistance of the second resistor is within acceptable limits.

16. The apparatus of claim 1, further comprising a visual indicator, wherein:

the power delivery path further comprises line side conductors and load side conductors;

the processor is further configured to initiate and control a simulation of a load side conductor fault and determine whether the fault detection circuit detects the resulting simulated fault; and

the visual indicator is a first color when power is present on the load side conductors, and changes to a second color to indicate improper operation of the apparatus or a fault related to the load side conductors.

17. The apparatus of claim 16, wherein the visual indicator is the output of a light pipe, further comprising:

a first light emitting diode (LED) powered by the load side conductors and emitting the first color; and

a second LED powered by the line side conductors and controlled by the processor, the second LED emitting a third color;

wherein the light pipe is configured to provide a combination of light from the first LED and the second LED as the visual indicator, and the second color is provided by a combination of the first color and the third color.

18. The apparatus of claim 17, wherein the third color is predominant over the first color, such that the second color at the visual indicator is substantially the third color emitted by the second LED.

19. The apparatus of claim 16, wherein the processor is further configured to selectively control an introduction of a current imbalance between two line side conductors during a fault simulation, wherein the processor is configured to control the introduction of a first current imbalance during a portion of a first power half-cycle and subsequently control the introduction of a second current imbalance during a portion of a second power half-cycle, and wherein the first power half-cycle and the second power half-cycle are separated in time by at least one power half-cycle.

20. The apparatus of claim 18, wherein the first power half-cycle is randomly either a positive polarity or a negative polarity.

21. The apparatus of claim 1, wherein the determination of whether the SCR is able to cause the interruption circuit to interrupt power delivery includes a determination of whether the SCR is capable of being latched during a power half-cycle in which the first trigger signal is provided.

22. The apparatus of claim 1, wherein the determination of whether the SCR is able to cause the interruption circuit to interrupt power delivery includes a determination of whether a voltage at the anode of the SCR is above a threshold.

23. The apparatus of claim 1, wherein the determination of whether the SCR is able to cause the interruption circuit to interrupt power delivery includes a determination of whether a voltage of the phase conductive path is in a positive half-cycle or a negative half-cycle.

24. The apparatus of claim 1, wherein the processor is further configured to monitor voltage or current of at least one circuit, wherein the determination of whether the SCR is able to cause the interruption circuit to interrupt power delivery includes a determination of whether there is a change in the monitored voltage or current.

25. The apparatus of claim 1, wherein the subsequent time is during an opposite-polarity half-cycle of the phase conductive path following the half-cycle in which the first trigger signal is provided to the SCR.

26. The apparatus of claim 1, wherein the first trigger signal and second trigger signal are received by the SCR through the same circuit.

27. The apparatus of claim 1, wherein the first trigger signal and second trigger signal are received by the SCR through different circuits.