Array substrate, display device and method for manufacturing array substrate

• US 9,759,958 B2
• Filed: 12/17/2013
• Issued: 09/12/2017
• Est. Priority Date: 08/30/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Choi, Hyunsic, Li, Hui, Xu, Zhiqiang, Um, Yoonsung
• Primary Examiner(s): DUONG, THOI V
• Application Number:
  US14/382,017
• Publication Number:
  US 20160291417A1
• Time in Patent Office: 1,365 Days
• Field of Search: 257 72, 257 59, 257E33062, 349139, 349141, 349 43, 349138, 349 33, 349143, 349187, 349110, 438158, 345 87, 345 92, 345103, 345 58
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134381 Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/124 interdigital
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

The array substrate comprises a pixel electrode located in a pixel area and a common electrode corresponding to the pixel area; and a first passivation layer provided between the common electrode and the pixel electrode; wherein the pixel electrode comprises a plurality of strip-shaped first pixel electrodes and strip-shaped second pixel electrodes which are alternately arranged at intervals; and the common electrode comprises a plurality of strip-shaped common electrodes which are spaced from each other; wherein ends of the plurality of strip-shaped first pixel electrodes are connected to each other to form a comb shape, and ends of the plurality of strip-shaped second pixel electrodes are connected to each other to form a comb shape; and the comb-shaped first pixel electrode and the comb-shaped second pixel electrode are spaced from each other.

Claims

1. An array substrate, comprising a pixel electrode located in a pixel area and a common electrode corresponding to the pixel area;

and a first passivation layer provided between the common electrode and the pixel electrode;

wherein the pixel electrode comprises a plurality of strip-shaped first pixel electrodes and a plurality of strip-shaped second pixel electrodes which are alternately arranged at intervals; and

the common electrode comprises a plurality of strip-shaped common electrodes which are spaced from each other;

wherein ends of the plurality of strip-shaped first pixel electrodes are connected to each other to form a comb-shaped first pixel electrode, and ends of the plurality of strip-shaped second pixel electrodes are connected to each other to form a comb-shaped second pixel electrode; and

the comb-shaped first pixel electrode and the comb-shaped second pixel electrode are spaced from each other, a projection of the pixel electrode onto the array substrate and a projection of the common electrode onto the array substrate do not overlap.

2. The array substrate according to claim 1, wherein the strip-shaped common electrode is arranged in the same direction as the strip-shaped first pixel electrode and the strip-shaped second pixel electrode;

and

each strip-shaped common electrode corresponds to a gap between the strip-shaped first pixel electrode and the strip-shaped second pixel electrode adjacent thereto, each strip-shaped first pixel electrode or strip-shaped second pixel electrode corresponds to a gap between two strip-shaped common electrodes adjacent thereto.

3. The array substrate according to claim 1, wherein the array substrate further comprises a data line;

the common electrode is located above the data line, and one of the plurality of strip-shaped common electrodes is provided above the data line; and

a second passivation layer is provided between the strip-shaped common electrode and the data line.

4. The array substrate according to claim 2, wherein the array substrate further comprises a data line;

the common electrode is located above the data line, and one of the plurality of strip-shaped common electrodes is provided above the data line; and

a second passivation layer is provided between the strip-shaped common electrode and the data line.

5. The array substrate according to claim 3, wherein the second passivation layer is made of a resin material.

6. The array substrate according to claim 3, wherein the strip-shaped common electrode provided above the data line has a width larger than that of the data line.

7. The array substrate according to claim 3, wherein the strip-shaped common electrode above the data line has a width larger than those of other strip-shaped common electrodes.

8. The array substrate according to claim 1, wherein the pixel electrode is provided above or below the common electrode.

9. A method for manufacturing an array substrate, comprising:

forming a first passivation layer on a substrate formed with a thin film transistor;

forming a common electrode layer on the substrate formed with the first passivation layer; and

fabricating the common electrode layer into a plurality of strip-shaped common electrodes which are spaced from each other,

forming a second passivation layer on the substrate formed with the strip-shaped common electrodes; and

forming patterns of a plurality of strip-shaped first pixel electrodes and a plurality of strip-shaped second pixel electrodes, which are alternately arranged at intervals, on the substrate formed with the second passivation layer;

wherein ends of patterns of the plurality of strip-shaped first pixel electrodes are connected to each other to form a pattern of a comb shaped first pixel electrode, and ends of patterns of the plurality of strip-shaped second pixel electrodes are connected to each other to form a pattern of a comb-shaped second pixel electrode; and

the pattern of the comb-shaped first pixel electrode and the pattern of the comb-shaped second pixel electrode are spaced from each other,

wherein a projection of the plurality of strip-shaped first pixel electrodes and the plurality of strip-shaped second pixel electrodes onto the array substrate and a projection of the plurality of strip-shaped common electrodes onto the array substrate do not overlap.

10. The method according to claim 9, wherein

the strip-shaped common electrode is arranged in the same direction as the strip-shaped first pixel electrode and the strip-shaped second pixel electrode;

and

each strip-shaped common electrode corresponds to a gap between the strip-shaped first pixel electrode and the strip-shaped second pixel electrode adjacent thereto, each strip-shaped first pixel electrode or strip-shaped second pixel electrode corresponds to a gap between two strip-shaped common electrodes adjacent thereto.

11. The method according to claim 9, wherein the step of fabricating the common electrode layer into a plurality of strip-shaped common electrodes which are spaced from each other comprises:

fabricating the common electrode layer into a plurality of strip-shaped common electrodes which are spaced from each other, wherein one of the plurality of strip-shaped common electrodes is provided above a data line of the array substrate; and

providing a first passivation layer between the strip-shaped common electrode and the data line.

12. A method for manufacturing an array substrate, comprising:

forming a first passivation layer on a substrate formed with a thin film transistor;

forming patterns of a strip-shaped first pixel electrode and a strip-shaped second pixel electrode, which are alternately arranged at intervals, on the substrate formed with the first passivation layer;

wherein ends of patterns of a plurality of strip-shaped first pixel electrodes are connected to each other to form a pattern of a comb-shaped first pixel electrode, and ends of patterns of a plurality of strip-shaped second pixel electrodes are connected to each other to form a pattern of a comb-shaped second pixel electrode; and

the pattern of the comb-shaped first pixel electrode and the pattern of the comb-shaped second pixel electrode are spaced from each other;

forming a second passivation layer on the substrate formed with the strip-shaped first pixel electrode and the strip-shaped second pixel electrode which are alternately arranged at intervals;

forming a common electrode layer on the substrate formed with the second passivation layer; and

fabricating the common electrode layer into a plurality of strip-shaped common electrodes which are spaced from each other,

wherein a projection of the plurality of strip-shaped first pixel electrodes onto the array substrate, a projection of the plurality of strip-shaped second pixel electrodes onto the array substrate and a projection of the plurality of strip-shaped common electrodes onto the array substrate do not overlap.

13. The method according to claim 12, wherein

the strip-shaped common electrode is arranged in the same direction as the strip-shaped first pixel electrode and the strip-shaped second pixel electrode;

and

each strip-shaped common electrode corresponds to a gap between the strip-shaped first pixel electrode and the strip-shaped second pixel electrode adjacent thereto, each strip-shaped first pixel electrode or strip-shaped second pixel electrode corresponds to a gap between two strip-shaped common electrodes adjacent thereto.