Enhanced dynamic memory management with intelligent current/power consumption minimization

• US 9,760,149 B2
• Filed: 01/08/2013
• Issued: 09/12/2017
• Est. Priority Date: 01/08/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Park, Hee Jun, Hofmann, Richard Gerard, Lee, Yong Ju
• Primary Examiner(s): Yen, Paul J
• Application Number:
  US13/736,268
• Publication Number:
  US 20140195837A1
• Time in Patent Office: 1,708 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

Claims

1. An electronic device, comprising:

a plurality of volatile memory devices; and

a processing circuit coupled to the plurality of volatile memory devices, wherein the processing circuit is configured to perform dynamic memory management by

obtaining a power conservation state current/power consumption for each volatile memory device in the plurality of volatile memory devices and determining between at least two sets of volatile memory devices of the plurality of volatile memory devices which set has a lower power conservation state current/power consumption, wherein the power conservation state current/power consumption includes dynamic power consumption;

copying data from a first set of the volatile memory devices, during a transition to a power-down state, to a second set of the volatile memory devices to reduce current/power consumption based on a determination that the second set of volatile memory devices has a lower power conservation state current/power consumption than the first set of volatile memory devices;

placing the first set of volatile memory devices into the power-down state to reduce power consumption, and

placing the second set of volatile memory devices into the power conservation state to reduce power consumption, wherein the power conservation state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

2. The device of claim 1, wherein the processing circuit is further configured to:

determine when to switch the first set of volatile memory devices into the power-down state after a period of inactivity.

3. The device of claim 1, wherein the power conservation state current/power consumption further includes leakage current/power consumption.

4. The device of claim 1, wherein the plurality of volatile memory devices are arranged in one or more channels, and the first set and second set of volatile memory devices are determined on a per channel basis.

5. The device of claim 4, wherein the data is copied between memory devices in the same channel.

6. The device of claim 1, wherein the power conservation state current/power consumption for each of the plurality of volatile memory devices is ascertained during a manufacturing stage or during an initialization stage.

7. The device of claim 1, further comprising:

a power management device coupled to the processing circuit and configured to ascertain the power conservation state current/power consumption for each of the plurality of volatile memory devices.

8. The device of claim 1, wherein the processing circuit is further configured to

compensate for temperature variations between the memory devices;

and

normalize the power conservation state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

9. The device of claim 1, further comprising:

a non-volatile storage device coupled to the processing circuit, the non-volatile storage device storing the power conservation state current/power consumption for each of the plurality of volatile memory devices.

10. The device of claim 1, wherein the processing circuit is further configured to perform dynamic memory management by

obtaining a power conservation state current/power consumption for each memory bank within each of the volatile memory devices of the plurality of volatile memory devices;

copying data from a first set of memory banks to a second set of memory banks within the same memory device of the second set of memory, where the second set of memory banks has lower power conservation state current/power consumption than the first set of memory banks; and

placing the first set of memory banks into the power-down state.

11. A method for performing dynamic memory management, comprising:

obtaining a power conservation state current/power consumption for each volatile memory device in a plurality of volatile memory devices and determining between at least two sets of volatile memory devices of the plurality of volatile memory devices which set has a lower power conservation state current/power consumption, wherein the power conservation state current/power consumption includes dynamic power consumption;

copying data from a first set of the volatile memory devices to a second set of the volatile memory devices, during a transition to a power-down state, to reduce current/power consumption based on a determination that the second set of volatile memory devices has a lower power conservation state current/power consumption than the first set of volatile memory devices;

placing the first set of volatile memory devices into the power-down state to reduce power consumption, and

placing the second set of volatile memory devices into the power conservation state to reduce power consumption, wherein the power conservation state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

12. The method of claim 11, further comprising:

determining when to switch the first set of volatile memory devices into the power-down state after a period of inactivity.

13. The method of claim 11, wherein the power conservation state current/power consumption further includes leakage current/power consumption.

14. The method of claim 11, further comprising:

compensating for temperature variations between the memory devices; and

normalizing the power conservation state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

15. The method of claim 11, wherein the first set of the volatile memory devices and the second set of the volatile memory devices are coupled to the same memory bus channel.

16. The method of claim 11, further comprising:

obtaining a power conservation state current/power consumption for each memory bank within each of the plurality of volatile memory devices;

copying data from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower power conservation state current/power consumption than the first set of memory banks; and

placing the first set of memory banks into the power-down state.