Stack pointer and memory access alignment control

• US 9,760,374 B2
• Filed: 06/28/2011
• Issued: 09/12/2017
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Grisenthwaite, Richard Roy
• Primary Examiner(s): Giroux, George
• Application Number:
  US13/067,805
• Publication Number:
  US 20120042136A1
• Time in Patent Office: 2,268 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.

Claims

1. Apparatus for processing data comprising:

processing circuitry responsive to program instructions to perform data processing operations;

a stack pointer register coupled to said processing circuitry and configured to store a stack pointer value indicative of an address within a memory of a stack data store;

stack alignment checking circuitry coupled to said processing circuitry and to said stack pointer register and configured to respond to a program instruction specifying a memory access to said stack data store at an address specified by said stack pointer value to detect if said stack pointer value matches a predetermined stack alignment condition;

alignment checking control circuitry coupled to said stack alignment checking circuitry and responsive to a stack configuration parameter to selectively disable said stack alignment checking circuitry independently of further alignment checking performed upon memory accesses.

2. Apparatus as claimed in claim 1, wherein said further alignment checking comprises alignment checking for all memory accesses.

3. Apparatus as claimed in claim 1, wherein said stack memory access is one of:

(i) a stack push operation storing one or more data values to said stack memory starting at a top of stack address specified by said stack pointer value and updating said stack pointer value to indicate a new top of stack address; and

(ii) a stack pop operation reading one or more data values from said stack memory starting at a top of stack address specified by said stack pointer value and updating said stack pointer value to indicate a new top of stack address.

4. Apparatus as claimed in claim 2, comprising general purpose alignment checking circuitry coupled to said processing circuitry and configured to respond to a program instruction specifying a general purpose access to said memory at any memory address to detect if said address matches a predetermined general purpose alignment condition.

5. Apparatus as claimed in claim 4, wherein said alignment checking control circuitry is coupled to said general purpose alignment checking circuitry and is responsive to a general configuration parameter to selectively disable said general purpose alignment checking circuitry independently of alignment checking performed by said stack alignment checking circuitry upon stack memory accesses using said stack pointer value.

6. Apparatus as claimed in claim 1, wherein said predetermined stack alignment condition comprises said stack pointer value is one of:

unconstrained;

an integer multiple of 2^N, where N is a non-zero integer value.

7. Apparatus as claimed in claim 6, wherein N is one of 3 and 4.

8. Apparatus as claimed in claim 4, wherein N is set under user control.

9. Apparatus as claimed in claim 1, comprising a plurality stack pointer registers each storing a respective stack pointer value and wherein said processing circuitry is configured to operate at a plurality exception levels each associated with a respective one of said plurality of stack pointer registers for use when said processing circuitry is operating at said exception level and having a respective stack configuration parameter for controlling whether or not stack alignment checking circuitry is disabled at that exception level.

10. Apparatus for processing data comprising:

processing means for performing data processing operations in response to program instructions;

stack pointer means for storing a stack pointer value, said stack pointer means being coupled to said processing means and said stack pointer value being indicative of an address within a memory of a stack data store;

stack alignment checking means for checking alignment, said stack alignment checking means being coupled to said processing means and to said stack pointer means and configured to respond to a program instruction specifying a memory access to said stack data store at an address specified by said stack pointer value to detect if said stack pointer value matches a predetermined stack alignment condition;

alignment checking control means for controlling alignment checking, said alignment checking control means being coupled to said stack alignment checking means and being responsive to a stack configuration parameter to selectively disable said stack alignment checking means independently of further alignment checking performed upon memory accesses.

11. A method of processing data comprising the steps of:

performing data processing operations in response to program instructions;

storing within a stack pointer register a stack pointer value indicative of an address within a memory of a stack data store;

in response to a program instruction specifying a memory access to said stack data store at an address specified by said stack pointer value, detecting if said stack pointer value matches a predetermined stack alignment condition;

in response to a stack configuration parameter, selectively omitting said detecting step independently of further alignment checking performed upon memory accesses.

12. A method as claimed in claim 11, wherein said further alignment checking comprises alignment checking for all memory accesses.

13. A method as claimed in claim 11, wherein said stack memory access is one of:

(i) a stack push operation storing one or more data values to said stack memory starting at a top of stack address specified by said stack pointer value and updating said stack pointer value to indicate a new top of stack address; and

(ii) a stack pop operation reading one or more data values from said stack memory starting at a top of stack address specified by said stack pointer value and updating said stack pointer value to indicate a new top of stack address.

14. A method as claimed in claim 11, comprising the steps of general purpose alignment checking circuitry responsive to a program instruction specifying a general purpose access to said memory at any memory address to detect if said address matches a predetermined general purpose alignment condition.

15. A method as claimed in claim 14, wherein in response to a general configuration parameter selectively disabling said general purpose alignment checking independently of alignment checking performed upon stack memory accesses using said stack pointer value.

16. A method as claimed in claim 11, wherein said predetermined stack alignment condition comprises said stack pointer value is one of:

unconstrained;

an integer multiple of 2^N, where N is a non-zero integer value.

17. A method as claimed in claim 16, wherein N is one of 3 and 4.

18. A method as claimed in claim 16, wherein N is set under user control.

19. A method as claimed in claim 11, comprising the steps of storing a plurality of stack pointer value in respective stack pointer registers and operating at a plurality exception levels each associated with a respective one of said plurality of stack pointer registers for use when said processing circuitry is operating at said exception level and having a respective stack configuration parameter for controlling whether or not stack alignment checking is performed at that exception level.

20. A virtual machine comprising a computer program stored on a non-transitory, computer-readable medium to control a computer to perform a method as claimed in claim 11.