Dynamically modifying a power/performance tradeoff based on a processor utilization
First Claim
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1. A processor comprising:
- a plurality of cores;
at least one graphics engine;
a shared cache memory; and
a power controller, the power controller including a policy switching circuit to dynamically update a power management policy, the power management policy selectable by a user from a plurality of policies provided by an operating system including a power saver policy, a balanced policy and a performance policy, to the performance policy when a ratio of a duration of a maximum performance state residency of the processor during an evaluation interval to a duration of an active state residency of the processor during the evaluation interval exceeds a threshold level.
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Abstract
In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
100 Citations
20 Claims
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1. A processor comprising:
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a plurality of cores; at least one graphics engine; a shared cache memory; and a power controller, the power controller including a policy switching circuit to dynamically update a power management policy, the power management policy selectable by a user from a plurality of policies provided by an operating system including a power saver policy, a balanced policy and a performance policy, to the performance policy when a ratio of a duration of a maximum performance state residency of the processor during an evaluation interval to a duration of an active state residency of the processor during the evaluation interval exceeds a threshold level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
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determining, in a circuit of a power controller of a multicore processor, an active state residency for a plurality of cores of the multicore processor during an evaluation interval; determining, in the circuit, a maximum performance state residency for the plurality of cores during the evaluation interval; determining, in the circuit, a ratio between the maximum performance state residency and the active state residency; and setting a power management policy based at least in part on the ratio. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A system comprising:
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a multicore processor including a plurality of cores and a power controller including circuitry to dynamically switch a power management policy for the multicore processor from a power saver policy to a performance policy based at least in part on a first comparison between an active state residency for the multicore processor and a maximum performance state residency for the multicore processor and a second comparison between a result of the first comparison and a threshold level; and a dynamic random access memory (DRAM) coupled to the multicore processor. - View Dependent Claims (19, 20)
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Specification