Private memory table for reduced memory coherence traffic
First Claim
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1. A method for memory coherence in a multiple processor system, the method comprising:
- generating by a virtual machine manager of a first processing node in the multiple processor system, a private region table associated with a processing core of the first processing node, wherein;
the private region table stores an entry identifying a memory region, associated with a virtual machine executing on the first processing node, which is stored remotely in memory of a second processing node,the entry includes a bitmask having a bit for each cache line of the memory region, andthe bit for a cache line of the memory region is set to a first value if the corresponding cache line is private to the virtual machine executing on the first processing node, or a second value if the cache line of the memory region is not private to the virtual machine;
responsive to a memory operation from the processing core in the first processing node of the multiple processor system resulting in a cache miss, checking the private region table associated with the processing core, wherein the memory operation attempts to access the memory region stored in memory of the second processing node of the multiple processor system;
responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, performing the memory operation on the second processing node without snooping the entire multiple processor system;
responsive to another processing core accessing a cache line of the memory region, setting a value of a corresponding bit in the bitmask of the en to the second value; and
invalidating the entry in the private region table in response to all bits in the bitmask for the memory region being set to the second value.
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Abstract
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.
63 Citations
11 Claims
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1. A method for memory coherence in a multiple processor system, the method comprising:
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generating by a virtual machine manager of a first processing node in the multiple processor system, a private region table associated with a processing core of the first processing node, wherein; the private region table stores an entry identifying a memory region, associated with a virtual machine executing on the first processing node, which is stored remotely in memory of a second processing node, the entry includes a bitmask having a bit for each cache line of the memory region, and the bit for a cache line of the memory region is set to a first value if the corresponding cache line is private to the virtual machine executing on the first processing node, or a second value if the cache line of the memory region is not private to the virtual machine; responsive to a memory operation from the processing core in the first processing node of the multiple processor system resulting in a cache miss, checking the private region table associated with the processing core, wherein the memory operation attempts to access the memory region stored in memory of the second processing node of the multiple processor system; responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, performing the memory operation on the second processing node without snooping the entire multiple processor system; responsive to another processing core accessing a cache line of the memory region, setting a value of a corresponding bit in the bitmask of the en to the second value; and invalidating the entry in the private region table in response to all bits in the bitmask for the memory region being set to the second value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification