Multiprocessor messaging system

• US 9,760,526 B1
• Filed: 09/30/2011
• Issued: 09/12/2017
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC IP Holdings Company LLC
• Inventors: Shubel, Paul A.
• Primary Examiner(s): Giroux, George
• Application Number:
  US13/251,155
• Time in Patent Office: 2,174 Days
• Field of Search: 712 28, 712 30, 712 32, 712220, 712225, 712 E9016
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

A multiprocessor system includes a first microprocessor and a second microprocessor. An external memory system is coupled to the first and second microprocessors and is configured to receive and temporarily store messages transferred between the first and second microprocessors. A first signaling pathway may be configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. A second signaling pathway may be configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The first signaling pathway may be independent of the second signaling pathway. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor.

Claims

1. A multiprocessor system comprising:

a first microprocessor;

a second microprocessor;

an external memory system coupled to the first and second microprocessors and configured to receive and temporarily store messages transferred between the first and second microprocessors, wherein the external memory system is physically separate from the first and second microprocessors;

a first signaling pathway for sending message transmission coordination signals from the first microprocessor to the second microprocessor, wherein the first signaling pathway is coupled to at least two flag registers included within the second microprocessor, wherein a first flag register of the at least two flag registers included within the second microprocessor is configured to receive an indicator that a message from the first microprocessor is waiting in the external memory system and a second flag register of the at least two flag registers included within the second microprocessor is configured to receive an indicator that a message from the second microprocessor was received by the first microprocessor; and

a second signaling pathway for sending message transmission coordination signals from the second microprocessor to the first microprocessor, wherein the second signaling pathway is coupled to at least two flag registers included within the first microprocessor, wherein a first flag register of the at least two flag registers included within the first microprocessor is configured to receive an indicator that a message from the second microprocessor is waiting in the external memory system and a second flag register of the at least two flag registers included within the first microprocessor is configured to receive an indicator that a message from the first microprocessor was received by the second microprocessor;

wherein the external memory system is compartmentalized into a first portion configured to receive messages from the first microprocessor for the second microprocessor and a second portion configured to receive messages from the second microprocessor for the first microprocessor;

wherein the first signaling pathway is independent of the second signaling pathway.

2. The multiprocessor system of claim 1 wherein the external memory system includes dynamic random access memory.

3. The multiprocessor system of claim 1 wherein the external memory system includes flash memory.

4. The multiprocessor system of claim 1 wherein the first portion of the external memory system is compartmentalized into a temporary storage area and a prioritized storage area and the external memory system is configured to:

process messages received by the temporary storage area from the first microprocessor for the second microprocessor,

categorize the processed messages into one of a plurality of priorities; and

store the categorized messages within the prioritized storage area.

5. The multiprocessor system of claim 4 wherein the second processor is configured to retrieve the categorized messages from the prioritized storage area of the first portion of the external memory system.

6. The multiprocessor system of claim 1 wherein the second portion of the external memory system is compartmentalized into a temporary storage area and a prioritized storage area and the external memory system is configured to:

process messages received by the temporary storage area from the second microprocessor for the first microprocessor,

categorize the processed messages into one of a plurality of priorities; and

store the categorized messages within the prioritized storage area.

7. The multiprocessor system of claim 6 wherein the first processor is configured to retrieve the categorized messages from the prioritized storage area of the second portion of the external memory system.

8. The multiprocessor system of claim 1 wherein at least one of the first and second microprocessors is a RISC microprocessor.

9. The multiprocessor system of claim 1 wherein at least one of the first and second microprocessors is a system services processor.

10. A computer-implemented method comprising:

receiving messages at an external memory system coupled to a first microprocessor and a second microprocessor, wherein the received messages are transferred between the first and second microprocessors, wherein the external memory system is physically separate from the first and second microprocessors;

temporarily storing the messages at the external memory system;

sending message transmission coordination signals from the first microprocessor to the second microprocessor via a first signaling pathway, wherein the first signaling pathway is coupled to at least two flag registers included within the second microprocessor, wherein first flag register of the at least two flag registers included within the second microprocessor is configured to receive an indicator that a message from the first microprocessor is waiting in the external memory system and a second flag register of the at least two flag registers included within the second microprocessor is configured to receive an indicator that a message from the second microprocessor was received by the first microprocessor; and

sending message transmission coordination signals from the second microprocessor to the first microprocessor via a second signaling pathway, wherein the second signaling pathway is coupled to at least two flag registers included within the first microprocessor, wherein a first flag register of the at least two flag registers included within the first microprocessor is configured to receive an indicator that a message from the second microprocessor is waiting in the external memory system and a second flag register of the at least two flag registers included within the first microprocessor is configured to receive an indicator that a message from the first microprocessor was received by the second microprocessor;

wherein the external memory system is compartmentalized into a first portion configured to receive messages from the first microprocessor for the second microprocessor and a second portion configured to receive messages from the second microprocessor for the first microprocessor;

wherein the first signaling pathway is independent of the second signaling pathway.

11. The computer-implemented method of claim 10 wherein the external memory system includes dynamic random access memory.

12. The computer-implemented method of claim 10 wherein the external memory system includes flash memory.

13. The computer-implemented method of claim 10 wherein the first portion of the external memory system is compartmentalized into a temporary storage area and a prioritized storage area and the external memory system is configured to:

process messages received by the temporary storage area from the first microprocessor for the second microprocessor,

categorize the processed messages into one of a plurality of priorities; and

store the categorized messages within the prioritized storage area.

14. The computer-implemented method of claim 13 wherein the second processor is configured to retrieve the categorized messages from the prioritized storage area of the first portion of the external memory system.

15. The computer-implemented method of claim 10 wherein the second portion of the external memory system is compartmentalized into a temporary storage area and a prioritized storage area and the external memory system is configured to:

process messages received by the temporary storage area from the second microprocessor for the first microprocessor,

categorize the processed messages into one of a plurality of priorities; and

store the categorized messages within the prioritized storage area.

16. The computer-implemented method of claim 15 wherein the first processor is configured to retrieve the categorized messages from the prioritized storage area of the second portion of the external memory system.

17. The computer-implemented method of claim 10 wherein at least one of the first and second microprocessors is a RISC microprocessor.

18. The computer-implemented method of claim 10 wherein at least one of the first and second microprocessors is a system services processor.