Multi-decoding method and multi-decoder for performing same

• US 9,761,232 B2
• Filed: 09/29/2014
• Issued: 09/12/2017
• Est. Priority Date: 09/27/2013
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jo, Seok-hwan, Son, Chang-yong, Kim, Do-hyung, Lee, Kang-eun, Lee, Si-hwa
• Primary Examiner(s): Leland, III, Edwin S
• Application Number:
  US15/024,266
• Publication Number:
  US 20160240198A1
• Time in Patent Office: 1,079 Days
• Field of Search: 704500
• CPC Class Codes: G10L 19/008 Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing

Abstract

A multi-decoding method, according to the present invention, comprises the steps of: receiving a plurality of bitstreams, dividing decoding modules for decoding the plurality of bitstreams according to a data amount of an instruction cache, and cross-decoding the plurality of bitstreams using each of the divided decoding modules.

Claims

1. A multi-decoding method comprising:

receiving a plurality of bitstreams;

dividing decoding modules for decoding the plurality of bitstreams according to an amount of data of an instruction cache; and

cross-decoding the plurality of bitstreams using each of the divided decoding modules.

2. The multi-decoding method of claim 1, wherein the cross-decoding of the plurality of bitstreams comprises consecutively decoding two or more bitstreams among the plurality of bitstreams using any one of the divided decoding modules.

3. The multi-decoding method of claim 2, wherein the cross-decoding of the plurality of bitstreams comprises consecutively decoding the two or more bitstreams among the plurality of bitstreams using instruction codes, which are cached in the instruction cache to execute the any one of the divided decoding modules.

4. A non-transitory computer-readable recording medium storing a program for causing a computer to perform the method of claim 2.

5. A non-transitory computer-readable recording medium storing a program for causing a computer to perform the method of claim 3.

6. The multi-decoding method of claim 1, wherein the cross-decoding of the plurality of bitstreams comprises:

caching some of instruction codes stored in a main memory to the instruction cache to execute any one of the divided decoding modules;

consecutively decoding two or more bitstreams among the plurality of bitstreams using the cached instruction codes; and

caching some of the instruction codes stored in the main memory to the instruction cache to execute another one of the divided decoding modules.

7. A non-transitory computer-readable recording medium storing a program for causing a computer to perform the method of claim 6.

8. A non-transitory computer-readable recording medium storing a program for causing a computer to perform the method of claim 1.

9. A multi-decoder comprising:

a plurality of decoders configured to separately decode a plurality of bitstreams, each decoder including at least one decoding module;

a main memory in which instruction codes necessary for decoding the plurality of bitstreams are stored;

an instruction cache in which instruction codes required by respective decoding modules among the instruction codes stored in the main memory are cached; and

a controller configured to divide the decoding modules according to an amount of data of the instruction cache and perform control so that the plurality of decoders cross-execute each of the divided decoding modules.

10. The multi-decoder of claim 9, wherein the controller causes two or more decoders among the plurality of decoders to consecutively execute any one of the divided decoding modules.

11. The multi-decoder of claim 10, wherein the controller causes the two or more decoders among the plurality of decoders to consecutively perform decoding using instruction codes, which are cached in the instruction cache to execute the any one of the divided decoding modules.

12. The multi-decoder of claim 9, wherein the controller is further configured to:

divide the decoding modules and cache the instruction codes for executing the divided decoding modules from the main memory to the instruction cache; and

cause the plurality of decoders to perform cross-decoding using the instruction codes cached in the instruction cache for each of the divided decoding modules.

13. The multi-decoder of claim 12, wherein, when the controller caches instruction codes corresponding to any one of the divided decoding modules in the instruction cache, the controller causes two or more decoders among the plurality of decoders to consecutively perform decoding using the instruction cache.

14. The multi-decoder of claim 12, wherein the instruction codes are stored in the main memory according to a processing sequence of the decoding modules.

15. The multi-decoder of claim 12, wherein the controller controls the plurality of decoders to perform the cross-decoding in units of frames of the plurality of bitstreams.

16. The multi-decoder of claim 12, wherein the controller does not divide the decoding modules when data amounts of the decoding modules are equal to or smaller than the data amount of the instruction cache.

17. The multi-decoder of claim 12, wherein the controller divides the decoding modules into a plurality of modules having data amounts equal to or smaller than the amount of data of the instruction cache when data amounts of the decoding modules are larger than the data amount of the instruction cache.

18. The multi-decoder of claim 9, wherein the plurality of bitstreams include bitstreams of one main audio signal and at least one associated audio signal.