Semiconductor memory device

• US 9,761,318 B1
• Filed: 08/31/2016
• Issued: 09/12/2017
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kondo, Shigeo
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/253,520
• Publication Number:
  US 20170263326A1
• Time in Patent Office: 377 Days
• Field of Search: 36518523, 36518524
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.

Claims

1. A semiconductor memory device, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells at intersections of the word lines and the bit lines;

a word line driver configured to apply a voltage to a selected word line among the plurality of word lines;

a sense amplifier circuit configured to detect the data of at least one of the memory cells; and

a controller configured to control the word line driver and the sense amplifier,

wherein a write sequence for writing first data to a selected memory cell connected to the selected word line includes a write loop that includes a write operation in which a write voltage is applied to the selected word line by the word line driver, and a verify operation during which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed by the controller,

based on second data to be written to a memory cell adjacent to the selected memory cell at a time later than the first data, the controller changes the reference voltage used for the verify operation of the selected memory cell, and

the adjacent memory cell is connected to a word line adjacent to the selected word line.

2. The semiconductor memory device according to claim 1, wherein

the controller selectively reduces the reference voltage used for completing writing to the selected memory cell based on the second data.

3. The semiconductor memory device of claim 2, wherein the adjacent word line is the next or previous word line to intersect the bit line connected to the selected memory cell.

4. The semiconductor memory device according to claim 1, wherein

the data to be written to a memory cell is writable at a plurality of data states and an erase state, and when the second data is data that is logically only one level higher than the erase state, the controller changes the reference voltage used for completing writing to the selected memory cell.

5. The semiconductor memory device according to claim 1, wherein

the word line driver is configured to raise the voltage of the selected word line each time the write loop is performed in one write sequence,

in the write sequence of the first data, when the second data is data other than predetermined data and the threshold voltage of the selected memory cell exceeds a second reference voltage that is less than a first reference voltage, in the next write loop the controller raises voltage of the bit line connected to the selected memory cell in which the threshold voltage exceeds the second reference voltage, and completes a write sequence to the selected memory cell when the threshold voltage of the selected memory cell exceeds the first reference voltage, and

in the write sequence of the first data, when the second data is the predetermined data and the threshold voltage of the selected memory cell exceeds the second reference voltage, a write sequence to the selected memory cell is completed.

6. The semiconductor memory device according to claim 1, further comprising:

a buffer storage unit configured to store data to be later stored in a plurality of the memory cells connected to the selected word line and the adjacent word line.

7. The semiconductor memory device according to claim 6, wherein

the word line driver is configured to raise the voltage of the selected word line each time the write loop is performed in one write sequence,

in the write sequence of the first data, when the second data is data other than predetermined data and the threshold voltage of the selected memory cell exceeds a second reference voltage that is less than a first reference voltage, in the next write loop the controller raises the voltage of the bit line connected to the selected memory cell in which the threshold voltage exceeds the second reference voltage, and completes a write sequence to the selected memory cell when the threshold voltage of the selected memory cell exceeds the first reference voltage, and

in the write sequence of the first data, when the second data is the predetermined data and the threshold voltage of the selected memory cell exceeds the second reference voltage, a write sequence to the selected memory cell is completed.

8. A semiconductor memory device, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells at intersections of the word lines and the bit lines;

a word line driver configured to apply a voltage to a selected word line among the plurality of word lines;

a sense amplifier circuit configured to detect the data of at least one of the memory cells; and

a controller configured to control the word line driver and the sense amplifier, wherein

a write sequence for writing first data to a selected memory cell connected to the selected word line includes a write loop that includes a write operation in which a write voltage is applied to the selected word line by the word line driver, and a verify operation during which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed by the controller,

based on second data to be written to a memory cell adjacent to the selected memory cell at a time later than the first data, the controller changes the reference voltage used for the verify operation of the selected memory cell,

the adjacent memory cell is connected to an adjacent bit line adjacent to at least one side of a selected bit line connected to the selected memory cell, and

the controller is configured to reduce the reference voltage used in the verify operation of the selected memory cell based on the second data.

9. The semiconductor memory device according to claim 8, wherein

when the threshold voltage of the second data is higher than the threshold voltage of the first data, the controller reduces the reference voltage used in a verify operation of the selected memory cell.

10. The semiconductor memory device according to claim 8, wherein

when the second data is data at logically two or more levels higher than the first data, the controller reduces the reference voltage used in a verify operation of the selected memory cell.

11. The semiconductor memory device according to claim 8, wherein

the adjacent memory cell is one of the memory cells on either side of the selected memory cell along the selected word line, and

when the second data in the adjacent memory cells is data at logically two or more levels higher than the first data, the controller reduces the reference voltage used in a verify operation of the selected memory cell.

12. The semiconductor memory device of claim 11, wherein the adjacent bit line is the next or previous bit line to intersect the word line along the selected bit line.

13. The semiconductor memory device according to claim 8, wherein

the word line driver is configured to raise the voltage of the selected word line each time the write loop is performed in one write sequence,

in the write sequence of the first data, when the second data is data other than predetermined data and the threshold voltage of the selected memory cell exceeds a second reference voltage that is less than a first reference voltage, in the next write loop the controller raises the voltage of the bit line connected to the selected memory cell in which the threshold voltage exceeds the second reference voltage, and completes a write sequence to the selected memory cell when the threshold voltage of the selected memory cell exceeds the first reference voltage, and

in the write sequence of the first data, when the second data is the predetermined data and the threshold voltage of the selected memory cell exceeds the second reference voltage, a write sequence to the selected memory cell is completed.

14. A semiconductor memory device, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells at intersections of the word lines and the bit lines;

a word line driver configured to apply a voltage to a selected word line among the plurality of word lines;

a sense amplifier circuit configured to detect the data of at least one of the memory cells; and

a controller configured to control the voltage applied to a memory cell by the word line driver in a plurality of steps, wherein each step has a greater voltage level than a prior step, and to control the voltage sensed in a memory cell by the sense amplifier, wherein

a write sequence for writing first data to a selected memory cell connected to the selected word line includes a write loop that includes a write operation in which a write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed by the controller, and

the controller is configured to modify the final voltage applied by the driver to a first memory cell located at an intersection of a word line and a bit line based upon the highest voltage to be later applied to a second memory cell at an adjacent intersection of a word line and a bit line.

15. The semiconductor memory device of claim 14, wherein the controller is configured to modify the final voltage applied by the driver to a first memory cell located at an intersection of a word line and a bit line by reducing the reference voltage used in the verify operation of the first memory cell when the data to be later written in any of a plurality of adjacent memory cells is data having a voltage of at least two or more levels higher than the first data.

16. The semiconductor memory device of claim 15, wherein the controller is configured to write data to each memory cell in a sequence of lower middle writing, foggy writing and fine writing, wherein the data is written by lower middle writing to a first memory cell, thereafter data is written to the first memory cell using foggy writing, and thereafter data is written to an adjacent memory cell using lower middle writing.