Reducing hot electron injection type of read disturb during read recovery phase in 3D memory

• US 9,761,320 B1
• Filed: 12/19/2016
• Issued: 09/12/2017
• Est. Priority Date: 12/19/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Lu, Ching-Huang, Zhao, Wei
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/383,852
• Time in Patent Office: 267 Days
• Field of Search: 32618502
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.

Claims

1. An apparatus, comprising:

a plurality of strings extending vertically in a stack, each string comprising a source end, a source side select gate transistor at the source end, a drain end, a dummy memory cell adjacent to a source side data memory cell, and a plurality of non-source side data memory cells between the source side data memory cell and the drain end;

a dummy word line connected to the dummy memory cells;

a plurality of data word lines comprising a source side data word line connected to the source side data memory cell and non-source side data word lines connected to the non-source side data memory cells; and

a control circuit, the control circuit configured to apply a voltage at a control gate read level to a selected data word line among the plurality of data word lines while sensing memory cells connected to the selected data word line and while applying a voltage at a read pass level to unselected data word lines among the plurality of data word lines, followed by ramping down a voltage of the non-source side data word line to a steady state voltage, followed by, after the ramping down the voltage of the non-source side data word line to the steady state voltage, ramping down a voltage of the source side data word line and the voltage of the dummy word line to the steady state voltage.

2. The apparatus of claim 1, wherein:

the selected data word line is the source side data word line.

3. The apparatus of claim 2, wherein:

the control circuit is configured to increase the voltage of the source side data word line from the control gate read level to the read pass level after the sensing, and to ramp down the voltage of the source side data word line from the read pass level.

4. The apparatus of claim 1, wherein:

the selected data word line is one of the non-source side data word lines.

5. The apparatus of claim 1, further comprising:

in each string, between the source end and the dummy memory cell, an additional dummy memory cell; and

an additional dummy word line connected to the additional dummy memory cells, wherein the control circuit is configured to ramp down a voltage of the additional dummy word line from the read pass level concurrently with the ramping down of the voltage of the source side data word line.

6. The apparatus of claim 1, wherein:

each string comprises a channel material; and

for each string, the channel material comprises an interface between epitaxial silicon and polysilicon between the dummy memory cell and the source side select gate transistor.

7. The apparatus of claim 1, wherein:

the ramping down of the voltage of the non-source side data word and the ramping down of the voltage of the source side data word line, is from the read pass level.

8. The apparatus of claim 7, wherein:

the ramping down of the voltage of the non-source side data word lines and the ramping down of the voltage of the source side data word line, is to 0 V.

9. The apparatus of claim 1, wherein:

one of the data word lines is adjacent to the source side data word line; and

the ramping down of the voltage of the non-source side data word lines causes at least some memory cells connected to the one of the data word lines to transition from a conductive state to a non-conductive state.

10. The apparatus of claim 1, wherein:

each string comprises a drain side select gate transistor; and

the control circuit is configured to ramp down a voltage of the source side select gate transistors and the drain side select gate transistors concurrently and no later than the ramping down the voltage of the non-source side word lines.

11. The apparatus of claim 1, wherein:

the control circuit operates according to a clock and is configured to perform the ramping down of the voltage of the source side data word line at least one clock cycle after the ramping down of the voltage of the non-source side data word lines.

12. The apparatus of claim 1, wherein:

the control circuit is configured to perform the sensing of the memory cells connected to the selected data word line in connection with a read operation or with a verify test of a programming operation.

13. The apparatus of claim 1, wherein:

the stack comprises alternating dielectric layers and conductive layers; and

the dummy word line and the plurality of data word lines are provided by the conductive layers.

20. The apparatus of claim 1, wherein:

the ramping down of the voltage of the source side data word line is concurrent with the ramping down of the voltage of the dummy word line.

14. A method, comprising:

applying a voltage to a selected data word line in a block while sensing memory cells connected to the selected data word line and while applying a voltage at a read pass level to unselected data word lines in the block and to a dummy word line in the block, wherein the dummy word line is at a source side of the block;

subsequently ramping down a voltage applied to data word lines which are not adjacent to the dummy word line to a steady state voltage; and

subsequently, after the ramping down the voltage applied to the data word lines which are not adjacent to the dummy word line to the steady state voltage, ramping down a voltage applied to the dummy word line and a voltage applied to a data word line which is adjacent to the dummy word line to the steady state voltage.

15. The method of claim 14, wherein:

the ramping down of the voltage applied to the data word line which is adjacent to the dummy word line and the voltage applied to the data word line which is adjacent to the dummy word line after the ramping down of the voltage applied to the data word lines which are not adjacent to the dummy word line, occurs independently of whether the selected data word line is the data word line which is adjacent to the dummy word line.

16. The method of claim 14, wherein:

the memory cells connected to the selected data word line and memory cells connected to the unselected word line are arranged in string;

each string comprises memory cells between a source side select gate transistor and a drain side select gate transistor; and

the method further comprises ramping down voltages of the source side select gate transistors and the drain side select gate transistors no later than the ramping down of the voltage applied to the data word lines which are not adjacent to the dummy word line.

17. An apparatus, comprising:

means for sensing data memory cells in a block; and

means for ramping down a voltage of a source side data word line to a steady state voltage concurrent with a ramping down of a dummy word line adjacent to the source side data word line to the steady state voltage, after ramping down a voltage of other data word lines in a block to the steady state voltage, and after the sensing of the data memory cells, wherein the source side data word line is at a source side of the block.

18. The apparatus of claim 17, wherein:

the means for ramping is independent of whether the data memory cells which are sensed are connected to the source side data word line.

19. The apparatus of claim 17, further comprising:

means for ramping down a voltage of a source side dummy word line in the block concurrent with the ramping down of the voltage of the source side data word line.