Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

• US 9,761,457 B2
• Filed: 03/21/2016
• Issued: 09/12/2017
• Est. Priority Date: 07/10/2006
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Zhou, Baosuo, Abatchev, Mirzafer K., Niroomand, Ardavan, Morgan, Paul A., Meng, Shuang, Greeley, Joseph Neil, Coppa, Brian J.
• Primary Examiner(s): RAYMOND, BRITTANY L
• Application Number:
  US15/076,474
• Publication Number:
  US 20160203993A1
• Time in Patent Office: 540 Days
• CPC Class Codes: H01L 21/0335 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Claims

1. A method comprising:

providing a layer to be etched, the layer to be etched having an outermost surface;

forming a plurality of patterns on the outermost surface of the layer to be etched apart from each other, each of the patterns including a top surface and first and second sidewall surfaces;

forming a spacer layer conformally over the patterns and the layer to be etched, the spacer layer including a plurality of first portions and a plurality of second portions, each of the first portions being over the top surface of an associated one of the patterns, and each of the second portions being between associated adjacent two of the patterns and including;

forming first and second parts over the first sidewall surface of one of the associated adjacent two of the patterns and the second sidewall surface of the other of the associated adjacent two of the patterns, respectively; and

forming a third part interfacing the first and second parts with each other;

performing planarization on each of the first and second parts of the second portion of each of the spacer layer to provide first and second planarized parts without planarizing the third part;

removing the third part of each of the second portions of the spacer layer to separate the first and second planarized parts from each other; and

patterning the layer to be etched by use of at least a part of each of the first and second planarized parts that have been separated from each other.

2. The method according to claim 1 wherein each of the first portions of the spacer layer are removed to expose the top surface of each of the patterns by the performing planarization.

3. The method according to claim 2 further comprising removing each of the patterns prior to the patterning the layer to be etched.

4. The method according to claim 1, wherein the removing the third part of each of the second portions of the spacer layer causes exposing an associated part of the outermost surface of the layer to be etched.

5. The method according to claim 1, wherein the performing planarization causes upper surfaces of the first and second parts to have substantially the same height.

6. The method according to claim 1, wherein the performing planarization comprises a CMP process.

7. The method according to claim 1, wherein the forming a plurality of patterns comprises:

forming a plurality of core patterns on the outermost surface of the layer to be etched apart from each other, each of the core patterns including third and fourth sidewall surfaces;

forming core sidewall spacers over the third and fourth sidewall surfaces of each of the core patterns; and

removing the core patterns so that the patterns include the core sidewall spacers.

8. The method according to claim 1, wherein the spacer layer is formed in such thickness that makes a space defined by the first, second and third parts.