Buried channel semiconductor device and method for manufacturing the same

• US 9,761,584 B2
• Filed: 06/05/2015
• Issued: 09/12/2017
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chia-Chung, Huang, Chi-Feng, Liang, Victor Chiang, Tsai, Fu-Huan, Hsieh, Hsieh-Hung, Yeh, Tzu-Jin, Tsai, Han-Min, Chu, Hong-Lin
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Booker, Vicki B
• Application Number:
  US14/732,661
• Publication Number:
  US 20160358911A1
• Time in Patent Office: 830 Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential

Abstract

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming one or more fins extending in a first direction over a substrate,

wherein the one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction;

forming a resist layer over the one or more fins;

forming openings in the resist layer to expose the first region of the one or more fins;

implanting a dopant in the first region of the one or more fins through the openings formed in the resist layer but not in the second regions;

forming a gate structure overlying the first region of the one or more fins; and

forming source/drains on the second regions of the one or more fins.

2. The method for manufacturing a semiconductor device of claim 1, wherein the dopant is an N-type dopant, selected from the group consisting of P, As, and Sb.

3. The method for manufacturing a semiconductor device of claim 1, wherein the dopant is a P-type dopant, selected from the group consisting of B, BF₂, Al, and Ga.

4. The method for manufacturing a semiconductor device of claim 1,

wherein a concentration of the dopant in the first region is about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup>.

5. The method for manufacturing a semiconductor device of claim 4, wherein the concentration of the dopant in the first region is about 1×

10¹⁸ atoms cm<sup>−

3</sup> to 2×

10¹⁸ atoms cm<sup>−

3</sup>.

6. The method for manufacturing a semiconductor device of claim 1, further comprising removing the resist layer after implanting the dopant.

7. The method for manufacturing a semiconductor device of claim 1, wherein a concentration of the dopant in the first region is about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup>.

8. The method for manufacturing a semiconductor device of claim 7, wherein the concentration of the dopant in the first region is about 1×

10¹⁸ atoms cm<sup>−

3</sup> to 2×

10¹⁸ atoms cm<sup>−

3</sup>.

9. A method for manufacturing a semiconductor device, comprising:

forming a plurality of fins extending in a first direction over a substrate,

wherein the plurality of fins include a first region along the first direction and second regions on both sides of the first region along the first direction;

implanting a dopant centered at region in the fins located at about 15 to 20 nm from a top of the fins and 3 to 7 nm in a fin thickness direction from a sidewall extending along the first direction of the fins in the first region of the fins but not in the second regions;

forming a gate structure overlying the first region of the fins; and

forming source/drains on the second regions of the fins.

10. The method for manufacturing a semiconductor device of claim 9, wherein the dopant is an N-type dopant, selected from the group consisting of P, As, and Sb.

11. The method for manufacturing a semiconductor device of claim 9, wherein the dopant is a P-type dopant, selected from the group consisting of B, BF₂, Al, and Ga.

12. The method for manufacturing a semiconductor device of claim 9, further comprising forming an isolation insulating layer between adjacent fins.

13. The method for manufacturing a semiconductor device of claim 9, wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

14. The method for manufacturing a semiconductor device of claim 9, wherein the source/drain regions are raised source/drain regions.

15. A method for manufacturing a semiconductor device, comprising:

forming a plurality of fins extending in a first direction over a substrate,

wherein the fins include a first region along the first direction and second regions on both sides of the first region along the first direction;

forming a resist layer over the fins;

forming openings in the resist layer to expose the first region of the fins prior to implanting a dopant;

subsequently implanting the dopant to a concentration in the first region of about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup> in the first region of the fins but not in the second regions; and

forming a gate structure overlying the first region of the fins.

16. The method for manufacturing a semiconductor device of claim 15, wherein the dopant is an N-type dopant, selected from the group consisting of P, As, and Sb.

17. The method for manufacturing a semiconductor device of claim 15, wherein the dopant is a P-type dopant, selected from the group consisting of B, BF₂, Al, and Ga.

18. The method for manufacturing a semiconductor device of claim 15, wherein the concentration of the dopant in the first region is about 1×

10¹⁸ atoms cm<sup>−

3</sup> to 2×

10¹⁸ atoms cm<sup>−

3</sup>.

19. The method for manufacturing a semiconductor device of claim 15, further comprising removing the resist layer after implanting the dopant.