Semiconductor device

• US 9,761,611 B2
• Filed: 02/05/2016
• Issued: 09/12/2017
• Est. Priority Date: 10/23/2012
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Vu, David
• Application Number:
  US15/016,451
• Publication Number:
  US 20160163742A1
• Time in Patent Office: 585 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region;

a source electrode over the oxide semiconductor layer;

a first drain electrode over the oxide semiconductor layer;

a second drain electrode over the oxide semiconductor layer;

a gate insulating film over the source electrode, the first drain electrode, and the second drain electrode;

a first gate electrode covering a first side surface of the oxide semiconductor layer;

a second gate electrode overlapping with the oxide semiconductor layer;

a third gate electrode overlapping with the oxide semiconductor layer; and

a fourth gate electrode covering a second side surface of the oxide semiconductor layer,

wherein the second gate electrode and the third gate electrode are positioned between the first gate electrode and the fourth gate electrode in a channel width direction, and

wherein the first side surface of the oxide semiconductor layer and the second side surface of the oxide semiconductor layer are opposed to each other in the channel width direction.

2. The semiconductor device according to claim 1,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are placed in substantially parallel to the channel width direction.

3. The semiconductor device according to claim 1,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are in contact with the gate insulating film.

4. The semiconductor device according to claim 1,

wherein the second gate electrode and the third gate electrode are separated from the first gate electrode and the fourth gate electrode, and

wherein the second gate electrode and the third gate electrode are separated from each other.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one selected from the group consisting of an In-based metal oxide, a Zn-based metal oxide, an In—

Zn-based metal oxide, and an In—

Ga—

Zn-based metal oxide.

6. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region;

a gate insulating film over the oxide semiconductor layer;

a first gate electrode covering a first side surface of the oxide semiconductor layer;

a second gate electrode overlapping with the oxide semiconductor layer;

a third gate electrode overlapping with the oxide semiconductor layer; and

a fourth gate electrode covering a second side surface of the oxide semiconductor layer,

wherein the second gate electrode and the third gate electrode are positioned between the first gate electrode and the fourth gate electrode in a channel width direction, and

wherein the first side surface of the oxide semiconductor layer and the second side surface of the oxide semiconductor layer are opposed to each other in the channel width direction.

7. The semiconductor device according to claim 6,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are placed in substantially parallel to the channel width direction.

8. The semiconductor device according to claim 6,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are in contact with the gate insulating film.

9. The semiconductor device according to claim 6,

wherein the second gate electrode and the third gate electrode are separated from the first gate electrode and the fourth gate electrode, and

wherein the second gate electrode and the third gate electrode are separated from each other.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises at least one selected from the group consisting of an In-based metal oxide, a Zn-based metal oxide, an In—

Zn-based metal oxide, and an In—

Ga—

Zn-based metal oxide.