Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration
First Claim
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1. An integrated circuit, comprising:
- a first FET and a second FET,wherein at least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET,at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively;
a dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel; and
the dopant concentration of the body of each of the first and second FETs has multiple peaks along the channel.
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Abstract
An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
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Citations
18 Claims
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1. An integrated circuit, comprising:
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a first FET and a second FET, wherein at least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET, at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively; a dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel; and the dopant concentration of the body of each of the first and second FETs has multiple peaks along the channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification