Method for fabricating a shield gate trench MOSFET

• US 9,761,695 B1
• Filed: 11/29/2016
• Issued: 09/12/2017
• Est. Priority Date: 05/31/2016
• Status: Active Grant

• Current Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Original Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Inventors: Fan, Rangxuan, Miao, Jinzheng
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US15/363,138
• Time in Patent Office: 287 Days
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a shield gate trench MOSFET, including the following steps: forming a hard mask layer and defining a gate forming region; forming a top trench by means of both anisotropic and isotropic etching; forming an oxidative barrier layer; etching back the oxidative barrier layer, and then forming a bottom trench by means of anisotropic etching; forming a bottom oxidative layer by means of thermal oxidative self-alignment; removing the oxidative barrier layer; forming a gate dielectric film; forming a first polysilicon layer; etching back the first polysilicon layer to form respectively therefrom a polysilicon gate and a bottom shield polysilicon; forming a inter-poly dielectric isolation layer; etching back the inter-poly dielectric isolation layer; forming a second polysilicon layer and forming a shield polysilicon by means of superposition with the bottom shield polysilicon.

Claims

1. A method for fabricating a shield gate trench metal-oxide semiconductor field-effect transistor (MOSFET), comprising the following steps for forming a gate structure thereof:

step one;

providing a semiconductor substrate, forming a hard mask layer on a surface of the semiconductor substrate, defining a gate forming region by means of lithography, and removing the hard mask layer in the gate forming region by means of etching;

step two;

with the etched hard mask layer as a mask, conducting a first etching, which being an anisotropic one, on the semiconductor substrate to form a top trench, and subsequently conducting a second etching, which being an isotropic one, on the semiconductor substrate, to render a width of the top trench to be greater than an opening width defined by the hard mask layer;

step three;

forming an oxidative barrier layer on an inner side surface of the top trench, and extending the oxidative barrier layer to a surface of the hard mask layer exterior to the top trench;

step four;

etching back the oxidative barrier layer to remove the oxidative barrier layer on a surface of a bottom of the top trench and on the surface of the hard mask layer, with the oxidative barrier layer on the side surface of the top trench remaining intact;

with the hard mask layer as a mask, conducting a third etching, which being an anisotropic one, on the semiconductor substrate on the bottom of the top trench to form a bottom trench;

step five;

conducting thermal oxidation on a bottom surface and a side surface of the bottom trench to form a bottom oxidative layer by means of self-alignment, with the oxidative barrier layer protecting the semiconductor substrate on the side surface of the top trench during an entire process of the thermal oxidation of the bottom oxidative layer;

step six;

removing the oxidative barrier layer;

step seven;

forming a gate dielectric film on the side surface of the top trench;

step eight;

conducting a first polysilicon growth to form a first polysilicon layer for completely filling in the bottom trench formed with the bottom oxidative layer, the first polysilicon layer in the top trench being situated in a side surface of the gate dielectric film, with the first polysilicon layer respectively on either side of the top trench having a distance one with another, and the first polysilicon layer being extended to the surface of the hard mask layer exterior to the top trench;

step nine;

conducting an etchback on the first polysilicon layer, with the etchback rendering the first polysilicon layer on the bottom trench to be lower than a top of the bottom oxidative layer and removing at the same time the first polysilicon layer exterior to the top trench, the portion of the first polysilicon layer on either side of the top trench subsequent to the etchback constituting a polysilicon gate, and the first polysilicon layer filling in the bottom trench subsequent to the etchback constituting a bottom shield polysilicon;

step ten;

forming a inter-poly dielectric isolation layer which is formed on a side surface of the polysilicon gate and on a surface of the bottom shield polysilicon and is extended to the surface of the hard mask layer exterior to the top trench;

step eleven;

etching back the inter-poly dielectric isolation layer for removing the inter-poly dielectric isolation layer on the surface of the bottom shield polysilicon;

step twelve;

conducting a second polysilicon growth to form a second polysilicon layer which completely fills in the top trench in a top of the bottom shield polysilicon and constitutes a top shield polysilicon, and the top shield polysilicon and the bottom shield polysilicon are in contact with one another and constitute a shield polysilicon.

2. The method for fabricating the shield gate trench MOSFET of claim 1, further comprising, subsequent to forming the gate structure, the following steps:

step thirteen;

removing the second polysilicon layer, the inter-poly dielectric isolation layer, and the hard mask layer exterior to the top trench, and exposing the surface of the semiconductor substrate;

step fourteen;

injecting ions to form a well region in the semiconductor substrate;

conducting heavily doped source ion implantation to form a source region on a surface of the well region;

conducting thermal annealing on the well region and the source region;

step fifteen;

forming an interlayer film, a contact hole and a positive metal layer on a positive side of the semiconductor substrate, etching the positive metal layer to form a source pole and a gate pole, the source pole being in contact with the source region and the shield polysilicon via the contact hole, and the gate pole being in contact with the polysilicon gate via the contact hole;

step sixteen;

thinning a reverse side of the semiconductor substrate, forming a heavily doped drain region, and forming a reverse metal layer on a reverse side of the drain region as a drain pole.

3. The method for fabricating the shield gate trench MOSFET of claim 1, wherein the semiconductor substrate is a silicon substrate, with a silicon epilayer being formed on a surface of the silicon substrate, and the top trench and the bottom trench are all situated inside the silicon epilayer.

4. The method for fabricating the shield gate trench MOSFET of claim 1, wherein the hard mask layer in step one is composed of an oxidative layer.

5. The method for fabricating the shield gate trench MOSFET of claim 1, wherein the oxidative barrier layer in step three is composed of a first oxidative layer and a second nitrite layer being successively superposed.

6. The method for fabricating the shield gate trench MOSFET of claim 1, wherein the gate dielectric film in step seven is a gate oxide.

7. The method for fabricating the shield gate trench MOSFET of claim 6, wherein the gate oxide is formed by means of thermal oxidation.

8. The method for fabricating the shield gate trench MOSFET of claim 1, wherein the inter-poly dielectric isolation layer in step ten is composed of another oxidative layer.

9. The method for fabricating the shield gate trench MOSFET of claim 8, wherein the inter-poly dielectric isolation layer is formed by means of thermal oxidation.

10. The method for fabricating the shield gate trench MOSFET of claim 2, wherein step fifteen, subsequent to forming an opening of the contact hole and prior to filling in a metal, further comprises a step of forming a well region contact region by means of heavy doping on a bottom of the contact hole in contact with the source region.