Self-aligned trench MOSFET and method of manufacture

• US 9,761,696 B2
• Filed: 03/20/2014
• Issued: 09/12/2017
• Est. Priority Date: 04/03/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Li, Jian, Chen, Kuo-In, Terril, Kyle
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): CHAN, CANDICE
• Application Number:
  US14/221,012
• Publication Number:
  US 20140206165A1
• Time in Patent Office: 1,272 Days
• Field of Search: 438 27
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

Claims

1. A method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

depositing a first semiconductor layer upon a semiconductor substrate, wherein the first semiconductor layer and the semiconductor substrate are doped with a first type of impurity;

doping a first portion of the first semiconductor layer with a second type of impurity;

etching a plurality of trenches in the first semiconductor layer;

forming a first dielectric layer on the wall of the plurality of trenches;

depositing a second semiconductor layer in the plurality of trenches;

forming a second dielectric layer over the second semiconductor layer in the plurality of trenches;

etching recessed mesas in the first semiconductor layer aligned by the first and second dielectric layers;

doping a second portion of the first semiconductor layer proximate the recessed mesas with a second type of impurity;

forming a plurality of source/body contact spacers above the recessed mesas aligned between the second dielectric layer in the trenches;

etching a plurality of source/body contact trenches between the source/body contact spacers, wherein the source body contact trenches extend through the second portion of the first semiconductor layer;

doping a third portion of the first semiconductor layer proximate the source/body contact trenches with the first type of impurity aligned by the source/body contact spacers; and

deposit a first metal layer in the source/body contact trenches aligned to the source/body contact spacers.

2. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 1, wherein a first set of the plurality of trenches are substantially parallel with respect to each other and a second set of the plurality of trenches are normal-to-parallel with respect to the first set of the plurality of trenches.

3. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 1, wherein the plurality of trenches are substantially parallel with respect to each other.

4. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1, further comprising forming a silicide on the second semiconductor layer in the plurality of trenches.

5. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1, wherein forming the second dielectric over the second semiconductor in the plurality of trenches comprises:

depositing the dielectric layer; and

removing excess dielectric until the first semiconductor layer is exposed and the second dielectric covers the first semiconductor layer in the plurality of trenches.

6. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1, wherein forming the plurality of source/body contact spacers comprises:

conformally depositing a third dielectric layer after doping the second portion of the first semiconductor layer; and

etching the third dielectric layer whereby the portions of the third dielectric layer substantially remain along vertical sides the second dielectric layer proximate the recessed mesas.