Bipolar transistor on high-resistivity substrate

• US 9,761,700 B2
• Filed: 06/28/2012
• Issued: 09/12/2017
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph
• Primary Examiner(s): Shingleton, Michael
• Application Number:
  US13/536,630
• Publication Number:
  US 20140003000A1
• Time in Patent Office: 1,902 Days
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

Systems and methods are disclosed for processing radio frequency (RF) signals using one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Claims

1. A semiconductor die comprising:

a plurality of elements of a front-end module integrated on the semiconductor die, the plurality of elements including a power amplifier, a switch, and a plurality of filters;

a bulk silicon substrate having a high-resistivity portion;

a silicon-germanium bipolar transistor disposed on the bulk silicon substrate above the high-resistivity portion of the bulk silicon substrate, the silicon-germanium bipolar transistor configured as the power amplifier, the bulk silicon substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the bulk silicon substrate further including a trench disposed adjacent to the low-resistivity well;

a complementary metal oxide semiconductor field-effect transistor device grown on the bulk silicon substrate; and

one or more capacitors disposed on the high-resistivity portion.

2. The semiconductor die of claim 1 wherein the silicon-germanium bipolar transistor conditions or creates electronic signals.

3. The semiconductor die of claim 1 wherein the silicon substrate includes a low-resistivity epitaxial layer adjacent to a first portion of a top surface of the substrate at least partially above the high-resistivity portion.

4. The semiconductor die of claim 3 wherein the low-resistivity epitaxial layer includes material from an implanted sub-collector region of the silicon-germanium bipolar transistor that has out-diffused during processing of the silicon-germanium bipolar transistor.

5. The semiconductor die of claim 3 wherein at least a second portion of the top surface of the substrate includes a high-resistivity crystal-lattice-destroying implant.

6. The semiconductor die of claim 5 wherein the second portion of the top surface of the substrate is greater than 1 μ

m from the silicon-germanium bipolar transistor.

7. The semiconductor die of claim 5 further comprising a passive device disposed above the high-resistivity crystal-lattice-destroying implant.

8. The semiconductor die of claim 1 wherein the bulk silicon substrate includes a counter-doped high-resistivity region.

9. The semiconductor die of claim 1 further comprising an active device and a passive device disposed on the substrate wherein the low-resistivity well is disposed at least partially between the silicon-germanium bipolar transistor device and both the active device and the passive device.

10. The semiconductor die of claim 1 wherein the high-resistivity portion has a resistivity value greater than 500 Ohm*cm.

11. The semiconductor die of claim 1 wherein the high-resistivity portion has a resistivity of approximately 1 kOhm*cm.

13. The semiconductor die of claim 1 wherein the power amplifier is a dual band power amplifier that includes a low-band power amplifier and a high-band power amplifier.

17. The semiconductor die of claim 8 further comprising a passive device disposed above the counter-doped high-resistivity region.

12. A radio-frequency module comprising:

a packaging substrate configured to receive a plurality of components;

a die mounted on the packaging substrate, the die having a plurality of elements of a front-end module integrated on the die, the plurality of elements including a power amplifier, a switch, and a plurality of filters, the die further having a high-resistivity substrate portion and one or more passive devices, the power amplifier including a silicon-germanium bipolar transistor disposed above the high resistivity substrate portion, the die including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the die further including a trench disposed adjacent to the low-resistivity well, a complementary metal oxide semiconductor field-effect transistor device grown on the packaging substrate, and one or more capacitors disposed on the high-resistivity substrate portion; and

a plurality of connectors configured to provide electrical connections between the die and the packaging substrate.

14. The radio-frequency module of claim 12 wherein the high-resistivity substrate portion includes a low-resistivity epitaxial layer formed adjacent to a first portion of a top surface of the high-resistivity substrate portion at least partially above the high-resistivity portion.

15. The radio-frequency module of claim 14 wherein the low-resistivity epitaxial layer includes material from an implanted sub-collector region of the silicon-germanium bipolar transistor that has out-diffused during a device manufacturing process for the silicon-germanium bipolar transistor.

16. The radio-frequency module of claim 14 wherein the high-resistivity substrate portion includes a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor.