Power MOSFET having planar channel, vertical current path, and top drain electrode

• US 9,761,702 B2
• Filed: 08/18/2016
• Issued: 09/12/2017
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Pu, Kui, Su, Shih-Tzung
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/240,831
• Publication Number:
  US 20160359029A1
• Time in Patent Office: 390 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7812 with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Claims

1. A transistor comprising

a substrate;

a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration;

a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;

a trench having a vertical sidewall adjoining the second layer;

a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;

a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;

a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage,

the gate having a vertical extension into the trench, the vertical extension facing the vertical sidewall and insulated from the sidewall;

a first electrode; and

a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a vertical current flows through the first layer and the second layer such that a current is conducted between the first electrode and the second electrode.

2. The transistor of claim 1 further comprising a vertical field plate in the trench, the vertical field plate facing the vertical sidewall and insulated from the sidewall.

3. The transistor of claim 2 wherein the vertical field plate is connected to the gate.

4. The transistor of claim 2 wherein the vertical field plate is connected to the second electrode.

5. The transistor of claim 2 wherein the vertical field plate is deeper than the well region.

6. The transistor of claim 2 wherein the vertical field plate and the second dopant concentration of the second layer are configured to enhance lateral depletion of the second layer in the transistor'"'"'s off-state so that the second layer is fully depleted at a breakdown voltage of the transistor.

7. The transistor of claim 2 wherein the vertical field plate surrounds the second layer.

8. The transistor of claim 1 wherein the vertical extension of the gate extends below the well region.

9. The transistor of claim 1 wherein the well region extends to the vertical sidewall.

10. The transistor of claim 9 wherein the vertical extension of the gate inverts a portion of the well region abutting the vertical sidewall.

11. The transistor of claim 1 further comprising an enhanced doping region of the first conductivity type between the well region and the vertical sidewall, and the vertical extension of the gate is insulated from and opposes the enhanced doping region for reducing on-resistance.

12. The transistor of claim 1 wherein the first electrode is formed on a bottom surface of the substrate.

13. The transistor of claim 12 wherein the substrate is of the first conductivity type, and wherein the transistor is a vertical MOSFET.

14. The transistor of claim 12 wherein the substrate is of the second conductivity type, and wherein the transistor is a vertical IGBT.

15. The transistor of claim 1 further comprising:

a highly doped buried layer of the first conductivity type between the substrate and the first layer, the buried layer having a third dopant concentration higher than the second dopant concentration; and

a vertical conductor extending through at least the first layer and to the buried layer,

wherein the first electrode is located on a top surface of the transistor, along with the second electrode, and contacts the vertical conductor for conducting current flowing through the buried layer.

16. The transistor of claim 15 wherein the vertical conductor comprises a highly doped sinker of the first conductivity type.

17. The transistor of claim 15 further comprising an insulating layer between the substrate and the buried layer.

18. The transistor of claim 17 further comprising an insulating trench extending through at least the first layer to the insulating layer.

19. The transistor of claim 18 wherein the insulating trench contains a vertical field plate.

20. The transistor of claim 1 wherein the first conductivity type is an N-type and the second conductivity type is a P-type.