Isolation of bulk FET devices with embedded stressors
First Claim
1. A method of isolating a field-effect transistor (FET) device, the method comprising:
- forming a layer of silicon germanium (SiGe) over a substrate;
fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe;
etching the silicon layer to define a channel region below the dummy gate stack;
forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack; and
filling the cavity with an oxide and a low K spacer material to isolate the channel region from the substrate.
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Abstract
A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.
42 Citations
18 Claims
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1. A method of isolating a field-effect transistor (FET) device, the method comprising:
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forming a layer of silicon germanium (SiGe) over a substrate; fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe; etching the silicon layer to define a channel region below the dummy gate stack; forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack; and filling the cavity with an oxide and a low K spacer material to isolate the channel region from the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A field-effect transistor (FET) device, comprising:
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a substrate; a channel region formed as a fin between a source region and a drain region on the substrate; a gate stack formed above the channel region, wherein the channel region is isolated from the substrate by an oxide and a low K spacer material; and a stressor formed on the substrate adjacent to the channel region, wherein the stressor includes an undoped portion on the substrate. - View Dependent Claims (15, 16, 17, 18)
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Specification